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21 条记录 (耗时 0.017 秒)

    Biomarkers of metabolic responses to hepatic drugs
    1.
    发明授权
    Biomarkers of metabolic responses to hepatic drugs 有权
    对肝脏药物的代谢反应的生物标记物

    公开(公告)号：US07807138B2

    公开(公告)日：2010-10-05

    申请号：US11840466

    申请日：2007-08-17

    申请人： Alvin Berger ,  Imran A. Shah

    发明人： Alvin Berger ,  Imran A. Shah

    IPC分类号： A61N49/00

    CPC分类号： G01N33/5014

    摘要： Methods for the measurement and prediction of response to hepatotoxicants and carcinogens through the detection of metabolites in a mammal are provided. The metabolites can be used as biomarkers, including efficacy biomarkers, surrogate biomarkers, and toxicity biomarkers. The methods find use for early prediction of toxicity, target identification/validation, and monitoring of drug efficacy.

    摘要翻译： 提供了通过检测哺乳动物代谢物测量和预测对肝毒素和致癌物质的反应的方法。 代谢物可用作生物标志物，包括功效生物标志物，替代生物标志物和毒性生物标志物。 该方法用于早期预测毒性，靶标鉴定/验证和药物疗效监测。

    Device for splitting a digital interlaced television signal into components
    5.
    发明授权
    Device for splitting a digital interlaced television signal into components 失效
    将数字互联电视信号分解成组件的设备

    公开(公告)号：US5239377A

    公开(公告)日：1993-08-24

    申请号：US898775

    申请日：1992-06-12

    申请人： Imran A. Shah ,  Rob A. Beuker

    发明人： Imran A. Shah ,  Rob A. Beuker

    IPC分类号： H04N7/00 ,  H04N7/01 ,  H04N7/015 ,  H04N7/26 ,  H04N19/00

    CPC分类号： H04N7/015 ,  H04N19/63

    摘要： Device for splitting a digital interlaced television signal into components in which interlaced frames are applied to a vertical low-pass filter (6). To prevent motion artefacts in the spatial signal thus obtained, the interlaced frame is also applied to a vertical high-pass filter (8). This vertical high-pass filter supplies a motion auxiliary signal which may have a small vertical bandwidth. When combining the spatial signal and the motion auxiliary signal, noticeable motion artefacts do not occur in the interlaced frame. The device may be used for deriving a standard television signal from a high-definition television (HDTV) signal and for compatible transmission of HDTV signals.

    Memory architecture and method of data organization optimized for hashing
    9.
    发明授权
    Memory architecture and method of data organization optimized for hashing 失效
    数据组织的内存架构和方法优化哈希

    公开(公告)号：US5339398A

    公开(公告)日：1994-08-16

    申请号：US913764

    申请日：1992-07-14

    申请人： Imran A. Shah ,  Brian C. Johnson

    发明人： Imran A. Shah ,  Brian C. Johnson

    IPC分类号： G06F17/30 ,  G06F12/02

    CPC分类号： G06F17/30949

    摘要： A hashing data storage and retrieval arrangement whose storage capacity is unaffected by collisions. A first memory serves as a hash index table, for storing pointers at each address location corresponding to a hash value generated by hashing a key data word. Each pointer is the address of a location in a second memory, which has a separate storage location for each key data word, its associated data, and a further pointer which is the address of the next key data word resulting from a collision during hashing. Preferably a pipeline register between the two memories permits hashing of a subsequent key data word while accessing of the second memory is still in progress.

    摘要翻译： 散列数据存储和检索布置，其存储容量不受碰撞影响。 第一存储器用作散列索引表，用于存储与通过散列密钥数据字生成的散列值相对应的每个地址位置处的指针。 每个指针是第二存储器中的位置的地址，其具有用于每个关键数据字及其关联数据的单独的存储位置，以及另外的指针，该指针是由于散列期间的碰撞产生的下一个关键数据字的地址。 优选地，两个存储器之间的流水线寄存器允许随后的密钥数据字的散列，同时第二存储器的访问仍在进行中。

    Fast multiplier architecture
    10.
    发明授权
    Fast multiplier architecture 失效
    快速乘法器架构

    公开(公告)号：US4864529A

    公开(公告)日：1989-09-05

    申请号：US916916

    申请日：1986-10-09

    申请人： Imran A. Shah ,  Arup K. Bhattacharya

    发明人： Imran A. Shah ,  Arup K. Bhattacharya

    IPC分类号： G06F7/52

    CPC分类号： G06F7/5334

    摘要： A digital multiplier circuit which implements a modified multiplier algorithm in binary form and can be implemented as a very large scale integrated circuit. The modified algorithm replaces the large summation required in a typical shift-and-add digital multiplier with the sum of smaller summation terms, both yielding the same product. The digital word representing one of the multiplicands is partitioned or sliced into groups of two or more bits. All possible values of each bit slice are pre-calculated and stored to derive partial products thereof by the other multiplicand. The summation of such partial products rather than of individual bit products reduces the number of partial adders by half or more, depending on the number of bits in each partition or slice.

    摘要翻译： 一种数字乘法器电路，其实现二进制形式的修正乘数算法，并可实现为非常大规模的集成电路。 经修改的算法将典型的移位和加数字乘法器中所需的大量求和与较小的求和项相加，两者产生相同的乘积。 表示被乘数之一的数字字被分割或分成两个或多个位的组。 预先计算和存储每个位片的所有可能的值以通过另一被乘数导出其部分乘积。 这种部分产品而不是单个位产品的总和取决于每个分区或分片中的位数，将部分加法器的数量减少了一半或更多。