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    Methods of forming a phase change memory device
    1.
    发明授权
    Methods of forming a phase change memory device 有权
    形成相变存储器件的方法

    公开(公告)号：US08187914B2

    公开(公告)日：2012-05-29

    申请号：US12731637

    申请日：2010-03-25

    申请人： Jin-Il Lee ,  Urazaev Vladimir ,  Jin-Ha Jeong ,  Seung-Back Shin ,  Sung-Lae Cho ,  Hyeong-Geun An ,  Dong-Hyun Im ,  Young-Lim Park ,  Jung-Hyeon Kim

    发明人： Jin-Il Lee ,  Urazaev Vladimir ,  Jin-Ha Jeong ,  Seung-Back Shin ,  Sung-Lae Cho ,  Hyeong-Geun An ,  Dong-Hyun Im ,  Young-Lim Park ,  Jung-Hyeon Kim

    IPC分类号： H01L21/20

    CPC分类号： H01L45/1616 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1683

    摘要： Provided are methods of forming a phase change memory device. A semiconductor device having a lower electrode and an interlayer insulating layer may be prepared. The lower electrode may be surrounded by the interlayer insulating layer. Source gases, a reaction gas and a purge gas may be injected into a process chamber of a semiconductor fabrication device to form a phase change material layer on a semiconductor substrate. The source gases may be simultaneously injected into the process chamber. The phase change material layer may be in contact with the lower electrode through the interlayer insulating layer. The phase change material layer may be etched to form a phase change memory cell in the interlayer insulating layer. An upper electrode may be formed on the phase change memory cell.

    摘要翻译： 提供形成相变存储器件的方法。 可以制备具有下电极和层间绝缘层的半导体器件。 下电极可以被层间绝缘层包围。 可以将源气体，反应气体和吹扫气体注入到半导体制造装置的处理室中，以在半导体衬底上形成相变材料层。 源气体可以同时注入到处理室中。 相变材料层可以通过层间绝缘层与下电极接触。 可以蚀刻相变材料层以在层间绝缘层中形成相变存储单元。 可以在相变存储单元上形成上电极。

    NONVOLATILE MEMORY DEVICE USING VARIABLE RESISTIVE ELEMENT
    2.
    发明申请
    NONVOLATILE MEMORY DEVICE USING VARIABLE RESISTIVE ELEMENT 有权
    使用可变电阻元件的非易失性存储器件

    公开(公告)号：US20110272663A1

    公开(公告)日：2011-11-10

    申请号：US13103013

    申请日：2011-05-06

    申请人： Hyeong-Geun An ,  Sung-Lae Cho ,  Ik-Soo Kim ,  Dong-Hyun Im ,  Eun-Hee Cho

    发明人： Hyeong-Geun An ,  Sung-Lae Cho ,  Ik-Soo Kim ,  Dong-Hyun Im ,  Eun-Hee Cho

    IPC分类号： H01L45/00

    CPC分类号： H01L45/04 ,  H01L27/2427 ,  H01L27/249 ,  H01L45/1226

    摘要： A nonvolatile memory device and a method of fabricating the same are provided. The nonvolatile memory device includes a conductive pillar that extends from a substrate in a first direction, a variable resistor that surrounds the conductive pillar, a switching material layer that surrounds the variable resistor, a first conductive layer that extends in a second direction, and a first electrode that extends in a third direction and contacts the first conductive layer and the switching material layer. Not one of the first, second, and third directions is parallel to another one of the first, second, and third directions.

    摘要翻译： 提供了一种非易失性存储器件及其制造方法。 非易失性存储器件包括从第一方向从衬底延伸的导电柱，围绕导电柱的可变电阻器，围绕可变电阻器的开关材料层，沿第二方向延伸的第一导电层，以及 第一电极，其在第三方向上延伸并接触第一导电层和开关材料层。 第一，第二和第三方向中没有一个平行于第一，第二和第三方向的另一个。

    Phase changeable memory cell array region and method of forming the same
    3.
    发明授权
    Phase changeable memory cell array region and method of forming the same 有权
    相变存储单元阵列区域及其形成方法

    公开(公告)号：US08039298B2

    公开(公告)日：2011-10-18

    申请号：US12617782

    申请日：2009-11-13

    申请人： Hyeong-Geun An ,  Hideki Horii ,  Sang-Yeol Kang

    发明人： Hyeong-Geun An ,  Hideki Horii ,  Sang-Yeol Kang

    IPC分类号： H01L21/06 ,  H01L21/00 ,  G11C11/00

    CPC分类号： H01L45/144 ,  H01L27/2436 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1293 ,  H01L45/165 ,  H01L45/1666

    摘要： A phase changeable memory cell array region includes a lower interlayer insulating layer disposed on a semiconductor substrate. The region also includes a plurality of conductive plugs disposed through the lower interlayer insulating layer. The region also includes a phase changeable material pattern operably disposed on the lower interlayer insulating layer, the phase changeable pattern covering at least two of the plurality of conductive plugs, wherein the phase changeable material pattern includes a plurality of first regions in contact with one or more of the plurality of conductive plugs and at least one second region interposed between the plurality of the first regions, wherein the at least one second region has a lower thermal conductivity than the plurality of first regions. The phase changeable memory cell array region also includes an upper interlayer insulating layer covering at least one of the phase changeable material pattern and the lower interlayer insulating layer. The region also includes conductive patterns disposed through the upper interlayer insulating layer and electrically connected to a plurality of predetermined regions of the plurality of first regions.

    摘要翻译： 相变存储单元阵列区域包括设置在半导体衬底上的下层间绝缘层。 该区域还包括穿过下层间绝缘层设置的多个导电插塞。 所述区域还包括可操作地设置在所述下层间绝缘层上的可相变材料图案，所述相变图案覆盖所述多个导电插塞中的至少两个，其中所述相变材料图案包括多个与第 多个导电插塞中的多个和插入在多个第一区域之间的至少一个第二区域，其中至少一个第二区域具有比多个第一区域更低的热导率。 相变存储单元阵列区域还包括覆盖相变材料图案和下层间绝缘层中的至少一个的上层间绝缘层。 该区域还包括通过上层间绝缘层设置并电连接到多个第一区域中的多个预定区域的导电图案。

    Methods of forming contact structures and semiconductor devices fabricated using contact structures
    4.
    发明授权
    Methods of forming contact structures and semiconductor devices fabricated using contact structures 有权
    形成接触结构的方法和使用接触结构制造的半导体器件

    公开(公告)号：US08021977B2

    公开(公告)日：2011-09-20

    申请号：US12627810

    申请日：2009-11-30

    申请人： Young-Lim Park ,  Hyeong-Geun An ,  Gyu-Hwan Oh ,  Dong-Ho Ahn ,  Jin-Il Lee

    发明人： Young-Lim Park ,  Hyeong-Geun An ,  Gyu-Hwan Oh ,  Dong-Ho Ahn ,  Jin-Il Lee

    IPC分类号： H01L21/4763 ,  H01L21/768

    CPC分类号： H01L21/76816 ,  H01L27/24

    摘要： Provided are methods of forming contact structures and semiconductor devices fabricated using the contact structures. The formation of a contact structure can include forming a first molding pattern on a substrate, forming an insulating layer to cover at least a sidewall of the first molding pattern, forming a second molding pattern to cover a sidewall of the insulating layer and spaced apart from the first molding pattern, removing a portion of the insulating layer between the first and second molding patterns to form a hole, and forming an insulating pattern between the first and second molding patterns, and forming a contact pattern in the hole.

    摘要翻译： 提供了形成使用接触结构制造的接触结构和半导体器件的方法。 接触结构的形成可以包括在基底上形成第一模制图案，形成绝缘层以覆盖至少第一模制图案的侧壁，形成第二模制图案以覆盖绝缘层的侧壁并与 第一模制图案，去除第一和第二模制图案之间的绝缘层的一部分以形成孔，并且在第一和第二模制图案之间形成绝缘图案，并在孔中形成接触图案。

    PRAMs having a plurality of active regions located vertically in sequence and methods of forming the same
    6.
    发明授权
    PRAMs having a plurality of active regions located vertically in sequence and methods of forming the same 有权
    具有多个有序区域的垂直位置的PRAM及其形成方法

    公开(公告)号：US07309885B2

    公开(公告)日：2007-12-18

    申请号：US11246863

    申请日：2005-10-07

    申请人： Jae-Hyun Park ,  Hyeong-Geun An ,  Su-Jin Ahn ,  Yoon-Jong Song ,  Hyung-Joo Youn ,  Kyu-Chul Kim

    发明人： Jae-Hyun Park ,  Hyeong-Geun An ,  Su-Jin Ahn ,  Yoon-Jong Song ,  Hyung-Joo Youn ,  Kyu-Chul Kim

    IPC分类号： H01L27/10

    CPC分类号： H01L27/2436 ,  H01L45/06 ,  H01L45/144

    摘要： There are provided PRAMS having a plurality of active regions located vertically in sequence and methods of forming the same. The PRAM and the method provide an approach to rapidly changing phase in a phase change layer pattern with a given design rule. A semiconductor substrate defining at least one reference active region is prepared in a cell array region and a peripheral circuit region. Other semiconductor substrates on a vertical line passing a main surface of the reference active region are located in sequence. The other semiconductor substrates define other active regions, respectively. A lower cell gate pattern is formed on the semiconductor substrate of the reference active region, and upper cell gate patterns are disposed on the other semiconductor substrates of the other active regions, respectively.

    摘要翻译： 提供了具有顺序定位的多个活性区域和其形成方法的PRAMS。 PRAM和该方法提供了用给定设计规则快速改变相变层图案中的相位的方法。 在单元阵列区域和外围电路区域中制备限定至少一个参考有源区的半导体衬底。 在通过参考有源区域的主表面的垂直线上的其它半导体衬底依次定位。 其他半导体衬底分别限定其它有源区。 在参考有源区的半导体衬底上形成下电池栅极图案，并且上电池栅极图案分别设置在其它有源区的其它半导体衬底上。

    Method of fabricating a ferroelectric memory device
    7.
    发明授权
    Method of fabricating a ferroelectric memory device 有权
    制造铁电存储器件的方法

    公开(公告)号：US06815227B2

    公开(公告)日：2004-11-09

    申请号：US10744378

    申请日：2003-12-22

    申请人： Hyeong-Geun An

    发明人： Hyeong-Geun An

    IPC分类号： H01L2100

    CPC分类号： H01L27/11502 ,  H01L27/11507 ,  H01L28/55

    摘要： A ferroelectric memory device and a method of fabricating the same are provided. The ferroelectric memory device includes at least two capacitor patterns and a plate line. Each of the capacitor patterns includes a lower electrode, a ferroelectric layer, and an upper electrode that are stacked on a semiconductor substrate. A top of the plate line is covered with an oxygen barrier layer, and a sidewall of the plate line is covered with an oxygen barrier spacer.

    摘要翻译： 提供了一种铁电存储器件及其制造方法。 铁电存储器件包括至少两个电容器图案和板线。 每个电容器图案包括堆叠在半导体衬底上的下电极，铁电层和上电极。 板线的顶部被氧阻挡层覆盖，并且板状线的侧壁被氧隔离隔离物覆盖。

    Ferroelectric memory device and method of forming the same
    8.
    发明授权
    Ferroelectric memory device and method of forming the same 失效
    铁电存储器件及其形成方法

    公开(公告)号：US06815226B2

    公开(公告)日：2004-11-09

    申请号：US10613102

    申请日：2003-07-07

    申请人： Kyu-Mann Lee ,  Yong-Tak Lee ,  Hyeong-Geun An

    发明人： Kyu-Mann Lee ,  Yong-Tak Lee ,  Hyeong-Geun An

    IPC分类号： H01L2100

    CPC分类号： H01L27/11502 ,  G11C11/22 ,  H01L27/11507 ,  H01L28/57

    摘要： The method of forming a ferroelectric memory device includes forming capacitor patterns over a substrate, each capacitor pattern having an adhesive assistant pattern, a lower electrode, a ferroelectric pattern, and an upper electrode. An oxygen barrier layer is formed over the substrate and is etched to expose a sidewall of the ferroelectric pattern but not a sidewall of the adhesive assistant pattern. Then, a thermal process for curing ferroelectricity of the ferroelectric pattern is performed.

    摘要翻译： 形成铁电存储器件的方法包括在衬底上形成电容器图案，每个电容器图案具有粘合剂辅助图案，下电极，铁电体图案和上电极。 在衬底上形成氧阻隔层，并且被蚀刻以暴露铁电图案的侧壁，而不是粘合助剂图案的侧壁。 然后，进行用于固化铁电型图案的铁电性的热处理。

    FRAM and method of fabricating the same
    9.
    发明授权
    FRAM and method of fabricating the same 有权
    FRAM及其制造方法

    公开(公告)号：US06686620B2

    公开(公告)日：2004-02-03

    申请号：US10109432

    申请日：2002-03-27

    申请人： Hyeong-Geun An ,  Soon-Oh Park

    发明人： Hyeong-Geun An ,  Soon-Oh Park

    IPC分类号： H01L27108

    CPC分类号： H01L28/65 ,  H01L27/10852 ,  H01L27/10882 ,  H01L28/57

    摘要： A FRAM having a ferroelectric capacitor comprises a cylindrical type bottom electrode. A ferroelectric film is thinly stacked over the bottom electrode, and the first portion of the top electrode formed over and conformal to the ferroelectric film. A void that is left between sidewalls of the first portion of the electrode over the ferroelectric film is then filled with fill material for a fill layer. The fill material of the fill layer is then planarized to be level with and expose an upper surface of the first portion of the top electrode. A second portion of the top electrode is then formed over the fill layer and in contact with the exposed, e.g. peripheral regions of the first portion of the electrode. The fill material of the fill layer may be formed of polysilicon, silicon oxide or other material such as another metal. Additionally, the fill layer may be formed of a fill material that has a superior gap fill capability or of a material that has a low stress relationship with respect to the capacitor's top metal.

    摘要翻译： 具有铁电电容器的FRAM包括圆柱形底部电极。 铁电体薄膜层叠在底部电极上，并且顶部电极的第一部分形成在铁电膜上并与其形成共形。 然后，在铁电体膜上的电极的第一部分的侧壁之间留下的空隙填充有用于填充层的填充材料。 然后将填充层的填充材料平坦化以与顶部电极的第一部分的上表面平齐并暴露。 然后，顶部电极的第二部分形成在填充层之上并与暴露的例如电极接触。 电极的第一部分的周边区域。 填充层的填充材料可以由多晶硅，氧化硅或其它材料例如另一种金属形成。 另外，填充层可以由具有优异间隙填充能力的填充材料或与电容器的顶部金属具有低应力关系的材料形成。