公开(公告)号：US20130175616A1

公开(公告)日：2013-07-11

申请号：US13781722

申请日：2013-02-28

Applicant: WON GI MIN ,  ZHIHONG ZHANG ,  HONGZHONG XU ,  JIANG-KAI ZUO

Inventor： WON GI MIN ,  ZHIHONG ZHANG ,  HONGZHONG XU ,  JIANG-KAI ZUO

IPC: H01L29/78

CPC classification number: H01L29/7823 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/0882 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/7816 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Breakdown voltage BVdss is enhanced and ON-resistance reduced in RESURF devices, e.g., LDMOS transistors, by careful charge balancing, even when body and drift region charge balance is not ideal, by: (i) providing a plug or sinker near the drain and of the same conductivity type extending through the drift region at least into the underlying body region, and/or (ii) applying bias Viso to a surrounding lateral doped isolation wall coupled to the device buried layer, and/or (iii) providing a variable resistance bridge between the isolation wall and the drift region. The bridge may be a FET whose source-drain couple the isolation wall and drift region and whose gate receives control voltage Vc, or a resistor whose cross-section (X, Y, Z) affects its resistance and pinch-off, to set the percentage of drain voltage coupled to the buried layer via the isolation wall.

公开(公告)号：US20050207077A1

公开(公告)日：2005-09-22

申请号：US10805119

申请日：2004-03-19

Applicant: Hongzhong Xu ,  Beth Baumert ,  Richard Ida

Inventor： Hongzhong Xu ,  Beth Baumert ,  Richard Ida

IPC: H01L27/02 ,  H01L29/732 ,  H02H9/00

CPC classification number: H01L27/0259 ,  H01L29/7322

Abstract: Methods and apparatus are provided an electrostatic discharge (ESD) protection device having a first terminal and a second terminal. The ESD protection device comprises a vertical transistor having a collector coupled to the first terminal, a base, and an emitter coupled to the second terminal. A zener diode has a first terminal coupled to the first terminal of the ESD protection device and a second terminal coupled to the base of the vertical transistor. Subsurface current paths are provided to redistribute current from a surface of the vertical transistor in an ESD event. The method comprises generating an ionization current when a zener diode breaks down during an ESD event. The ionization current density from a surface zener diode region is reduced. The ionization current enables a transistor to dissipate the ESD event.

Abstract translation: 提供了一种具有第一端子和第二端子的静电放电（ESD）保护装置的方法和装置。 ESD保护装置包括垂直晶体管，其具有耦合到第一端子的集电极，基极和耦合到第二端子的发射极。 齐纳二极管具有耦合到ESD保护装置的第一端子的第一端子和耦合到垂直晶体管的基极的第二端子。 提供地下电流路径以在ESD事件中从垂直晶体管的表面重新分配电流。 该方法包括当在ESD事件期间齐纳二极管发生故障时产生电离电流。 来自表面齐纳二极管区域的电离电流密度降低。 电离电流使晶体管能够消散ESD事件。

公开(公告)号：US20050093073A1

公开(公告)日：2005-05-05

申请号：US11000584

申请日：2004-12-01

Applicant: Michael Baird ,  Richard Ida ,  James Whitfield ,  Hongzhong Xu ,  Sopan Joshi

Inventor： Michael Baird ,  Richard Ida ,  James Whitfield ,  Hongzhong Xu ,  Sopan Joshi

IPC: H01L20060101 ,  H01L21/00 ,  H01L23/62 ,  H01L27/02 ,  H01L27/04 ,  H01L29/76

CPC classification number: H01L27/0277 ,  H01L27/0266

Abstract: Systems and methods are described for a low-voltage electrostatic discharge clamp. A resistor pwell-tied transistor may be used as a low-voltage ESD clamp, where the body of the transistor is coupled to the source by a resistor, thereby reducing a DC leakage current and minimizing latch-ups in the transistor while maintaining effective ESD performance.

Abstract translation: 对于低压静电放电钳描述了系统和方法。 电阻阱连接晶体管可以用作低电压ESD钳位，其中晶体管的主体通过电阻器耦合到源极，从而降低DC漏电流并最小化晶体管中的闩锁，同时保持有效的ESD 性能。

公开(公告)号：US08487398B2

公开(公告)日：2013-07-16

申请号：US12835900

申请日：2010-07-14

Applicant: Hongzhong Xu ,  Zhihong Zhang ,  Jiang-Kai Zuo

Inventor： Hongzhong Xu ,  Zhihong Zhang ,  Jiang-Kai Zuo

IPC: H01L21/70

CPC classification number: H01L29/94 ,  H01L29/66181

Abstract: A semiconductor device includes an isolated p-type well, wherein the isolated p-type well is a first electrode of a capacitor device; a capacitor dielectric on the isolated p-type well; a p-type polysilicon electrode over the capacitor dielectric, wherein the p-type polysilicon electrode is a second electrode of the capacitor device; a first p-type contact region in the isolated p-type well, laterally extending from a first sidewall of the p-type polysilicon electrode; a second p-type contact region in the isolated p-type well, laterally extending from a second sidewall of the p-type polysilicon electrode, opposite the first sidewall of the p-type polysilicon electrode, wherein a portion of the isolated p-type well between the first and second p-type contact regions is under the p-type polysilicon electrode and the capacitor dielectric; and an n-type isolation region surrounding the isolated p-type well. This device may be conveniently coupled to a fringe capacitor.

Abstract translation: 半导体器件包括隔离的p型阱，其中隔离的p型阱是电容器器件的第一电极; 隔离p型阱上的电容器电介质; 电容器电介质上的p型多晶硅电极，其中p型多晶硅电极是电容器器件的第二电极; 分离的p型阱中的第一p型接触区，从p型多晶硅电极的第一侧壁横向延伸; 在隔离的p型阱中的第二p型接触区域，从p型多晶硅电极的第二侧壁横向延伸，与p型多晶硅电极的第一侧壁相对，其中一部分隔离的p型 第一和第二p型接触区之间的阱在p型多晶硅电极和电容器电介质之下; 以及围绕隔离p型阱的n型隔离区。 该装置可以方便地连接到边缘电容器。

公开(公告)号：US20120012970A1

公开(公告)日：2012-01-19

申请号：US12835900

申请日：2010-07-14

Applicant: HONGZHONG XU ,  ZHIHONG ZHANG ,  JIANG-KAI ZUO

Inventor： HONGZHONG XU ,  ZHIHONG ZHANG ,  JIANG-KAI ZUO

IPC: H01L27/07 ,  H01L21/02 ,  H01L29/06

CPC classification number: H01L29/94 ,  H01L29/66181

Abstract: A semiconductor device includes an isolated p-type well, wherein the isolated p-type well is a first electrode of a capacitor device; a capacitor dielectric on the isolated p-type well; a p-type polysilicon electrode over the capacitor dielectric, wherein the p-type polysilicon electrode is a second electrode of the capacitor device; a first p-type contact region in the isolated p-type well, laterally extending from a first sidewall of the p-type polysilicon electrode; a second p-type contact region in the isolated p-type well, laterally extending from a second sidewall of the p-type polysilicon electrode, opposite the first sidewall of the p-type polysilicon electrode, wherein a portion of the isolated p-type well between the first and second p-type contact regions is under the p-type polysilicon electrode and the capacitor dielectric; and an n-type isolation region surrounding the isolated p-type well. This device may be conveniently coupled to a fringe capacitor.

Abstract translation: 半导体器件包括隔离的p型阱，其中隔离的p型阱是电容器器件的第一电极; 隔离p型阱上的电容器电介质; 电容器电介质上的p型多晶硅电极，其中p型多晶硅电极是电容器器件的第二电极; 分离的p型阱中的第一p型接触区，从p型多晶硅电极的第一侧壁横向延伸; 在隔离的p型阱中的第二p型接触区域，从p型多晶硅电极的第二侧壁横向延伸，与p型多晶硅电极的第一侧壁相对，其中一部分隔离的p型 第一和第二p型接触区之间的阱在p型多晶硅电极和电容器电介质之下; 以及围绕隔离p型阱的n型隔离区。 该装置可以方便地连接到边缘电容器。

公开(公告)号：US07164566B2

公开(公告)日：2007-01-16

申请号：US10805119

申请日：2004-03-19

Applicant: Hongzhong Xu ,  Beth A. Baumert ,  Richard T. Ida

Inventor： Hongzhong Xu ,  Beth A. Baumert ,  Richard T. Ida

IPC: H02H9/00 ,  H01L23/62

CPC classification number: H01L27/0259 ,  H01L29/7322

Abstract: Methods and apparatus are provided an electrostatic discharge (ESD) protection device having a first terminal and a second terminal. The ESD protection device comprises a vertical transistor having a collector coupled to the first terminal, a base, and an emitter coupled to the second terminal. A zener diode has a first terminal coupled to the first terminal of the ESD protection device and a second terminal coupled to the base of the vertical transistor. Subsurface current paths are provided to redistribute current from a surface of the vertical transistor in an ESD event. The method comprises generating an ionization current when a zener diode breaks down during an ESD event. The ionization current density from a surface zener diode region is reduced. The ionization current enables a transistor to dissipate the ESD event.

Abstract translation: 提供了一种具有第一端子和第二端子的静电放电（ESD）保护装置的方法和装置。 ESD保护装置包括垂直晶体管，其具有耦合到第一端子的集电极，基极和耦合到第二端子的发射极。 齐纳二极管具有耦合到ESD保护装置的第一端子的第一端子和耦合到垂直晶体管的基极的第二端子。 提供地下电流路径以在ESD事件中从垂直晶体管的表面重新分配电流。 该方法包括当在ESD事件期间齐纳二极管发生故障时产生电离电流。 来自表面齐纳二极管区域的电离电流密度降低。 电离电流使晶体管能够消散ESD事件。

公开(公告)号：US06844597B2

公开(公告)日：2005-01-18

申请号：US10361469

申请日：2003-02-10

Applicant: Michael Baird ,  Richard T. Ida ,  James D. Whitfield ,  Hongzhong Xu ,  Sopan Joshi

Inventor： Michael Baird ,  Richard T. Ida ,  James D. Whitfield ,  Hongzhong Xu ,  Sopan Joshi

IPC: H01L20060101 ,  H01L21/00 ,  H01L23/62 ,  H01L27/02 ,  H01L27/04 ,  H01L29/76

CPC classification number: H01L27/0277 ,  H01L27/0266

Abstract: Systems and methods are described for a low-voltage electrostatic discharge clamp. A resistor pwell-tied transistor may be used as a low-voltage ESD clamp, where the body of the transistor is coupled to the source by a resistor, thereby reducing a DC leakage current and minimizing latch-ups in the transistor while maintaining effective ESD performance.

Abstract translation: 对于低压静电放电钳描述了系统和方法。 电阻阱连接晶体管可以用作低电压ESD钳位，其中晶体管的主体通过电阻器耦合到源极，从而降低DC漏电流并最小化晶体管中的闩锁，同时保持有效的ESD 性能。

公开(公告)号：US09041103B2

公开(公告)日：2015-05-26

申请号：US13781722

申请日：2013-02-28

Applicant: Won Gi Min ,  Zhihong Zhang ,  Hongzhong Xu ,  Jiang-Kai Zuo

Inventor： Won Gi Min ,  Zhihong Zhang ,  Hongzhong Xu ,  Jiang-Kai Zuo

IPC: H01L29/772 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7823 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/0882 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/7816 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Breakdown voltage BVdss is enhanced and ON-resistance reduced in RESURF devices, e.g., LDMOS transistors, by careful charge balancing, even when body and drift region charge balance is not ideal, by: (i) providing a plug or sinker near the drain and of the same conductivity type extending through the drift region at least into the underlying body region, and/or (ii) applying bias Viso to a surrounding lateral doped isolation wall coupled to the device buried layer, and/or (iii) providing a variable resistance bridge between the isolation wall and the drift region. The bridge may be a FET whose source-drain couple the isolation wall and drift region and whose gate receives control voltage Vc, or a resistor whose cross-section (X, Y, Z) affects its resistance and pinch-off, to set the percentage of drain voltage coupled to the buried layer via the isolation wall.

Abstract translation: 即使在身体和漂移区域电荷平衡不理想的情况下，即使在（i）在漏极附近提供插头或沉降片，即使通过仔细的电荷平衡，RESURF器件（例如LDMOS晶体管）中的击穿电压BVdss也能够降低导通电阻， 和/或（ii）将偏置Viso施加到耦合到器件掩埋层的周围横向掺杂隔离壁，和/或（iii）提供可变的 隔离墙和漂移区之间的电阻桥。 该桥可以是FET，其漏极耦合隔离壁和漂移区，并且其栅极接收控制电压Vc，或者其截面（X，Y，Z）影响其电阻和夹断的电阻器，以设置 通过隔离壁耦合到掩埋层的漏极电压的百分比。

公开(公告)号：US07701012B2

公开(公告)日：2010-04-20

申请号：US11678962

申请日：2007-02-26

Applicant: Hongzhong Xu ,  Chai Ean Gill ,  James D. Whitfield ,  Jinman Yang

Inventor： Hongzhong Xu ,  Chai Ean Gill ,  James D. Whitfield ,  Jinman Yang

IPC: H01L23/62

CPC classification number: H01L27/0259 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electrostatic discharge (ESD) protection clamp (61) for I/O terminals (22, 23) of integrated circuits (ICs) (24) comprises an NPN bipolar transistor (25) coupled to an integrated Zener diode (30). Variations in the break-down current-voltage characteristics (311, 312, 313, 314) of multiple prior art ESD clamps (31) in different parts of the same IC chip is avoided by forming the anode (301) of the Zener (30) in the shape of a base-coupled P+ annular ring (75) surrounded by a spaced-apart N+ annular collector ring (70) for the cathode (302) of the Zener (30). Even though an angled implant (51, 86, 98) used to form the N+ annular collector ring (70) causes location dependent variations in the width (531, 532) of the Zener space charge (ZSC) region (691, 692), the improved annular shaped clamp (61) always has a portion that initiates break-down at the design voltage so that variations in the width (531, 532) of the ZSC region (691, 692) do not cause significant variations in the clamp's current-voltage characteristics (611, 612, 613, 614).

Abstract translation: 用于集成电路（IC）（24）的I / O端子（22,23）的静电放电（ESD）保护夹具（61）包括耦合到集成齐纳二极管（30）的NPN双极晶体管（25）。 通过形成齐纳二极管（30）的阳极（301）避免同一IC芯片的不同部分的多个现有技术ESD钳位电路（31）的分解电流 - 电压特性（311,312,313,314）的变化 ）形成为由用于齐纳（30）的阴极（302）的间隔开的N +环形集电环（70）围绕的基底耦合的P +环形环（75）的形状。 即使用于形成N +环形集电环（70）的成角度的植入物（51,86,98）在齐纳空间电荷（ZSC）区域（691,692）的宽度（531,532）中引起位置相关的变化， 改进的环形夹具（61）总是具有在设计电压下启动分解的部分，使得ZSC区域（691,692）的宽度（531,532）的变化不会引起钳位电流的显着变化 - 电压特性（611,612,613,614）。

公开(公告)号：US07368786B2

公开(公告)日：2008-05-06

申请号：US11078026

申请日：2005-03-11

Applicant: Hongzhong Xu ,  Richard T. Ida ,  Vijay Parthasarathy

Inventor： Hongzhong Xu ,  Richard T. Ida ,  Vijay Parthasarathy

IPC: H01L23/58 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L27/0266 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/7835

Abstract: Methods and apparatus for ESD protection of LDMOS devices are provided. The apparatus comprises two LDMOS devices, with source, drain and gate contacts parallel coupled. One is the protected device and the other is the protecting device. Each has source region, drain region, gate, first body well region containing the source, second body well region containing the drain and separated from the first body well region by a drift region, an isolation region separated from the first and second body well regions and a buried layer contacting the isolation region. The protecting device has a further region of the same type as the drain, coupling the drain to the isolation region. Its drain connection is made via a contact to its isolation region rather than its drain region. The drift region of the protecting device is desirably smaller and the isolation-body well separation larger than for the protected device.

Abstract translation: 提供了LDMOS器件的ESD保护方法和设备。 该装置包括两个LDMOS器件，源极，漏极和栅极触点并联耦合。 一个是受保护的设备，另一个是保护设备。 每个具有源极区，漏极区，栅极，包含源极的第一体阱区域，含有漏极的第二体阱区域和通过漂移区域与第一体阱区域分离的隔离区域，与第一和第二体阱区域分离的隔离区域 以及与隔离区域接触的掩埋层。 保护装置具有与漏极相同类型的另一区域，将漏极耦合到隔离区域。 其漏极连接通过与其隔离区而不是漏极区的接触进行。 保护装置的漂移区域希望更小，并且隔离体阱分离比对于受保护的装置大。