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公开(公告)号：US20240310790A1
公开(公告)日：2024-09-19
申请号：US18598768
申请日：2024-03-07
发明人： Diansheng ZHANG
摘要： A clock display method, a computer device, a storage medium are provided. The method includes: performing time calibration by display driver chip based on local temporal information and processor temporal information to obtain calibrated temporal information; determining rotation angles of respective hand graphics forming display clock face according to the calibrated temporal information; retrieving a clock face image with no hands and at least one hand graphic which are locally stored; overlaying the at least one hand graphic onto the clock face image with no hands according to rotation angle of each hand graphic to obtain a clock face image corresponding to the calibrated temporal information; obtaining a background image issued by video processor, overlaying the clock face image onto the background image to obtain display clock face data, then transmitting the display clock face data to display screen to show the calibrated temporal information.
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2.发明授权公开(公告)号：US12093168B2
公开(公告)日：2024-09-17
申请号：US18077413
申请日：2022-12-08
发明人： Liwen Zhou , Guanfang Xiang , Yunfeng Zhou , Yifei Zhang
CPC分类号： G06F11/3676 , G06F8/53 , G06F8/77 , G06F9/30058 , G06F9/3844 , G06F11/3616 , G06F11/364
摘要： The present disclosure relates to a conditional branch coverage calculation method and device, computer apparatus, storage medium and computer program product. The method includes: acquiring code types of uncovered conditional branch code lines in target code, and acquiring comment information corresponding to the uncovered conditional branch code lines according to the code type; acquiring coverage parameter corresponding to the uncovered conditional branch code lines according to the comment information corresponding to the uncovered conditional branch code lines; and calculating a conditional branch coverage corresponding to the target code according to the coverage parameters corresponding to the uncovered conditional branch code lines and a total number of conditional branch code lines in the target code.
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3.发明公开公开(公告)号：US20240211307A1
公开(公告)日：2024-06-27
申请号：US18240168
申请日：2023-08-30
发明人： Bojun SHI , Zeqin ZHOU
CPC分类号： G06F9/4881 , G06F9/3877
摘要： The present application relates to a graphics processing unit (GPU) performance analysis method and a computer device, and a storage medium. The method includes: submitting a GPU task queue generated by a central processing unit (CPU) to a GPU; the GPU task queue including a plurality of GPU tasks sorted by processing start moments, each of the GPU tasks being configured with respective access addresses of a plurality of storage spaces required to be accessed when the GPU task is processed; processing the plurality of GPU tasks through the GPU according to a processing time sequence of each GPU task in the task queue; and acquiring, for a memory access procedure required in a GPU task processing procedure, execution performance reference information of the GPU and/or the CPU for each GPU task according to access time information generated by the CPU and the GPU for the memory access procedure.
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公开(公告)号：US20240184704A1
公开(公告)日：2024-06-06
申请号：US18524706
申请日：2023-11-30
发明人： Huaisheng ZHANG , Zhongyu TAO , Yuefan ZHANG
IPC分类号： G06F12/0868 , G06F5/01 , G06F7/523 , G06F7/535 , G06F12/0873
CPC分类号： G06F12/0868 , G06F5/01 , G06F7/523 , G06F7/535 , G06F12/0873
摘要： A method and an apparatus for reading cache data, and a storage medium are provided. The method includes: receiving a read instruction; converting at least one type of address offset position corresponding to the read instruction into a coupled address offset position according to a preset rule; performing a matching operation in a data group according to the coupled address offset position which corresponds to the at least one type of address offset position and obtaining corresponding cache data; reading the cache data obtained through matching. This method is able to simultaneously perform matching operations and reading operations for at least two combined address offset positions, thereby greatly improving data reading efficiency and doubling cache data reading throughput without significantly increasing hardware logic. Furthermore, this configuration is applicable to read-only cache, read-write cache, and write-only cache, possessing great versatility.
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公开(公告)号：US20240127526A1
公开(公告)日：2024-04-18
申请号：US18225493
申请日：2023-07-24
发明人： Jing FENG , Ziwen ZHU , Pengcheng YU , Lihao YANG
摘要： The present disclosure relates to a texture sampling method and apparatus based on merge processing of texel requests. The present disclosure merges target texel requests in the same cache line together, which reduces the number of cache hit tests. A pressure on the cache of next level to process texel requests may be significantly reduced, and the speed of texture sampling may be increased. The method includes: creating a texture sampling request, where the texture sampling request includes a pixel to be processed; obtaining multiple target texel requests based on pixel coordinates of the pixel to be processed; performing a merge processing on the multiple target texel requests according to a preset rule, and obtaining a merge table of texel requests; sequentially performing cache hit tests on the multiple target texel requests to obtain target texels based on the valid cache lines in the merge table of texel requests.
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公开(公告)号：US20240289048A1
公开(公告)日：2024-08-29
申请号：US18226687
申请日：2023-07-26
发明人： Zhulin CHANG , Huaisheng ZHANG , Xin JIN
IPC分类号： G06F3/06
CPC分类号： G06F3/0656 , G06F3/0604 , G06F3/0673
摘要： Disclosed are method and apparatus for loading task data, a computer device, a storage medium, and a computer program product. The method includes: analyzing various types of buffers involved in a task after the task is initiated, and determining whether each of the buffers satisfies a preset read-only buffer condition; determining a buffer satisfying the read-only buffer condition as a read-only buffer; mapping the read-only buffer into a matched read-only storage space based on space information of the read-only storage space and size information of the read-only buffer, and obtaining corresponding read-only mapping information; and loading task data in the read-only buffer into the matched read-only storage space based on the read-only mapping information. With the method, the loading efficiency of task data can be improved.
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7.发明公开公开(公告)号：US20240276025A1
公开(公告)日：2024-08-15
申请号：US18441463
申请日：2024-02-14
发明人： Cong ZHU , Wu Hao , Jinjing Li
IPC分类号： H04N19/89 , H04N19/169 , H04N19/172 , H04N19/174 , H04N19/70 , H04N19/80 , H04N19/91
CPC分类号： H04N19/89 , H04N19/172 , H04N19/174 , H04N19/188 , H04N19/70 , H04N19/80 , H04N19/91
摘要： A control method/system for bit stream parsing error detection in a video hardware decoder including performing a bit stream security range detection on the obtained video stream to obtain a first detection result, performing a bit stream extremum detection on the obtained video stream to obtain a second detection result, an performing an anomaly detection on the process of bit stream parsing on the video stream, and performing an exception handling or a frame reset on the video stream according to the results of the anomaly detection based on the first detection result and the second detection result.
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8.发明公开公开(公告)号：US20240129547A1
公开(公告)日：2024-04-18
申请号：US18189255
申请日：2023-03-24
发明人： Ao MEI , Chuanchuan ZHU , Wei WANG
IPC分类号： H04N19/89 , H04N19/176 , H04N19/182
CPC分类号： H04N19/89 , H04N19/176 , H04N19/182
摘要： Disclosed is a method and a device for decompressing Demura compensation value based on random-access bit stream. The method includes reading a target compression code corresponding to a target pixel set according to a screen refresh instruction in response to the screen refresh instruction, and decoding the target compression code to obtain Demura compensation values.
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9.发明公开公开(公告)号：US20240020094A1
公开(公告)日：2024-01-18
申请号：US18222101
申请日：2023-07-14
发明人： Yuqin YU , Yaohui ZENG , Renyu BIAN , Huaisheng ZHANG
IPC分类号： G06F7/523
CPC分类号： G06F7/523
摘要： Multiplication-accumulation method and apparatus, a processor, and a computer program product are provided. The method includes: when a logical operation unit performs single-precision floating-point number multiplication-accumulation operation, combining two half-precision multiplier-accumulators in each single-precision multiplication-accumulation unit to perform the multiplication-accumulation operation on to-be-processed single-precision floating-point numbers to obtain corresponding single-precision multiplication-accumulation results, a total of N multiplication-accumulation results being obtained; and when the logical operation unit performs half-precision floating-point number multiplication-accumulation operation, performing, by each half-precision multiplier-accumulator, the multiplication-accumulation operation on to-be-processed half-precision floating-point numbers to obtain corresponding half-precision multiplication-accumulation results, a total of 2N multiplication-accumulation results being obtained. Utilization of the multiplier-accumulators is improved.
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10.发明公开公开(公告)号：US20240013469A1
公开(公告)日：2024-01-11
申请号：US18219441
申请日：2023-07-07
发明人： Lei LI , Fengxia WU
CPC分类号： G06T15/005 , G06T11/001 , G06T2210/32 , G06T2210/44
摘要： Programmable pixel blending method and apparatus, computer device, storage medium and computer program product are provided. The method includes: performing rasterization on a first triangle, a second triangle, and a third triangle via the raster unit to obtain triangle coverage information of each triangle; sending the triangle coverage information to the warp assembly unit and the warp reorder unit respectively; assembling, by the warp assembly unit, the first triangle and the second triangle into a first warp, and requesting a warp from a warp request interface based on information of the first warp; executing the first warp based on a warp information cache, a warp synchronization unit, the warp reorder unit, the pixel operation unit, the interpolation unit, and the execution unit; after the first warp is executed, continuing to assemble, by the warp assembly unit, the third triangle and completing a rendering of the third triangle.
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