公开(公告)号：US08332607B2

公开(公告)日：2012-12-11

申请号：US12183229

申请日：2008-07-31

Applicant: Chih Wei Tsai ,  Chuang Cheng ,  Yung Li Ji ,  Shih Chieh Tai ,  Chih Cheng Tu ,  Fuja Shone

Inventor： Chih Wei Tsai ,  Chuang Cheng ,  Yung Li Ji ,  Shih Chieh Tai ,  Chih Cheng Tu ,  Fuja Shone

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC classification number: G06F13/4239 ,  Y02D10/14 ,  Y02D10/151

Abstract: A non-volatile memory storage device has a non-volatile memory, e.g., a flash memory, and a controller coupled to the non-volatile memory. The controller comprises a plurality of control circuits and an arbitration circuit. Each control circuit is configured to generate a request to update the chip-enable (CE) signals for non-volatile memory, and the arbitration circuit is configured to determine when the requests are acknowledged. The arbitration circuit generates acknowledge signals to the control circuits when all of the requests of the control circuits have been received by the arbitration circuit. The CE signals for non-volatile memory are updated when requests are acknowledged.

Abstract translation: 非易失性存储器存储设备具有非易失性存储器，例如闪存，以及耦合到非易失性存储器的控制器。 控制器包括多个控制电路和仲裁电路。 每个控制电路被配置为产生用于更新用于非易失性存储器的芯片使能（CE）信号的请求，并且仲裁电路被配置为确定何时请求被确认。 当仲裁电路已经接收到控制电路的所有请求时，仲裁电路向控制电路产生确认信号。 当请求被确认时，更新用于非易失性存储器的CE信号。

公开(公告)号：US20120233401A1

公开(公告)日：2012-09-13

申请号：US13043334

申请日：2011-03-08

Applicant: Hsingho LIU ,  Fuja SHONE ,  Chuang CHENG ,  Yu-Shuen TANG

Inventor： Hsingho LIU ,  Fuja SHONE ,  Chuang CHENG ,  Yu-Shuen TANG

IPC: G06F12/00

CPC classification number: G06F13/1605

Abstract: An embedded memory system is disclosed. A main interface is configured to communicate with an electronic system via a main bus. A memory-sharing auxiliary interface is configured to communicate with the electronic system via a memory-sharing auxiliary bus. An arbiter is configured to arbitrate among the main interface, the memory-sharing auxiliary interface, a primary memory, and a secondary memory. Accordingly, the electronic system is capable of sharing either the primary memory or the secondary memory via the memory-sharing auxiliary interface and the memory-sharing auxiliary bus, and the embedded memory system is capable of sharing a system memory of the electronic system via the memory-sharing auxiliary interface and the memory-sharing auxiliary bus.

Abstract translation: 公开了一种嵌入式存储器系统。 主界面被配置为经由主总线与电子系统进行通信。 存储器共享辅助接口被配置为经由存储器共享辅助总线与电子系统通信。 仲裁器被配置为在主界面，存储器共享辅助接口，主存储器和辅助存储器之间进行仲裁。 因此，电子系统能够经由存储器共享辅助接口和存储器共享辅助总线共享主存储器或辅助存储器，并且嵌入式存储器系统能够经由该存储器共享辅助总线共享电子系统的系统存储器 内存共享辅助接口和内存共享辅助总线。

公开(公告)号：US08095724B2

公开(公告)日：2012-01-10

申请号：US12026400

申请日：2008-02-05

Applicant: Yung Li Ji ,  Chia Chen Chang ,  Chih Nan Yen ,  Fuja Shone

Inventor： Yung Li Ji ,  Chia Chen Chang ,  Chih Nan Yen ,  Fuja Shone

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC classification number: G06F12/0246 ,  C07D401/12 ,  G06F2212/7201 ,  G06F2212/7211

Abstract: A method of wear leveling for a non-volatile memory is disclosed. A non-volatile memory is divided into windows and gaps, with each gap between two adjacent windows. The windows comprise physical blocks mapped to logical addresses, and the gaps comprise physical blocks not mapped to logical addresses. The windows are shifted through the non-volatile memory in which the mapping to the physical blocks in the window to be shifted is changed to the physical blocks in the gap.

Abstract translation: 公开了一种用于非易失性存储器的磨损均衡的方法。 非易失性存储器分为窗口和间隙，两个相邻窗口之间的每个间隙。 窗口包括映射到逻辑地址的物理块，并且间隙包括未映射到逻辑地址的物理块。 窗口移动通过非易失性存储器，在该非易失性存储器中，将要移位的窗口中的物理块的映射改变为间隙中的物理块。

公开(公告)号：US20100088458A1

公开(公告)日：2010-04-08

申请号：US12245093

申请日：2008-10-03

Applicant: YU MAO KAO ,  YUNG LI JI ,  CHIH NAN YEN ,  FUJA SHONE

Inventor： YU MAO KAO ,  YUNG LI JI ,  CHIH NAN YEN ,  FUJA SHONE

IPC: G06F12/02 ,  G06F12/00 ,  G06F12/10

CPC classification number: G06F12/04 ,  G06F12/0246 ,  G06F2212/1016 ,  Y02D10/13

Abstract: An operation method of a memory includes the steps of calculating an offset of sequential write commands and the beginning of pages of a block of a non-volatile memory; shifting the block by the offset; and directly writing data from a host to the pages except the first and last pages of the block by the sequential write commands. In an embodiment, the pages are logical pages providing optimal writing efficiency and are determined before calculating the offset. The step of shifting the block by the offset is to increase corresponding logical block addresses (LBA) in the pages by the offset.

Abstract translation: 存储器的操作方法包括以下步骤：计算顺序写入命令的偏移和非易失性存储器的块的开头; 将块移动偏移; 并且通过顺序写入命令直接将数据从主机写入除块的第一页和最后一页之外的页面。 在一个实施例中，页面是提供最佳写入效率的逻辑页面，并且在计算偏移量之前确定。 通过偏移移位块的步骤是通过偏移增加页面中的对应逻辑块地址（LBA）。

公开(公告)号：US20100030933A1

公开(公告)日：2010-02-04

申请号：US12183229

申请日：2008-07-31

Applicant: Chih Wei Tsai ,  Chuang Cheng ,  Yung Li Ji ,  Shih Chieh Tai ,  Chih Cheng Tu ,  Fuja Shone

Inventor： Chih Wei Tsai ,  Chuang Cheng ,  Yung Li Ji ,  Shih Chieh Tai ,  Chih Cheng Tu ,  Fuja Shone

IPC: G06F13/12 ,  G06F12/02

CPC classification number: G06F13/4239 ,  Y02D10/14 ,  Y02D10/151

Abstract: A non-volatile memory storage device has a non-volatile memory, e.g., a flash memory, and a controller coupled to the non-volatile memory. The controller comprises a plurality of control circuits and an arbitration circuit. Each control circuit is configured to generate a request to update the chip-enable (CE) signals for non-volatile memory, and the arbitration circuit is configured to determine when the requests are acknowledged. The arbitration circuit generates acknowledge signals to the control circuits when all of the requests of the control circuits have been received by the arbitration circuit. The CE signals for non-volatile memory are updated when requests are acknowledged.

Abstract translation: 非易失性存储器存储设备具有非易失性存储器，例如闪存，以及耦合到非易失性存储器的控制器。 控制器包括多个控制电路和仲裁电路。 每个控制电路被配置为产生用于更新用于非易失性存储器的芯片使能（CE）信号的请求，并且仲裁电路被配置为确定何时请求被确认。 当仲裁电路已经接收到控制电路的所有请求时，仲裁电路向控制电路产生确认信号。 当请求被确认时，更新用于非易失性存储器的CE信号。

公开(公告)号：US20090259819A1

公开(公告)日：2009-10-15

申请号：US12100136

申请日：2008-04-09

Applicant: YEN MING CHEN ,  SHIH CHIEH TAI ,  YUNG LI JI ,  CHIH NAN YEN ,  FUJA SHONE

Inventor： YEN MING CHEN ,  SHIH CHIEH TAI ,  YUNG LI JI ,  CHIH NAN YEN ,  FUJA SHONE

IPC: G06F12/02 ,  G06F13/00 ,  G06F12/00

CPC classification number: G06F13/4239

Abstract: A method of wear leveling for a non-volatile memory is performed as follows. First, the non-volatile memory is divided into a plurality of zones including at least a first zone and a second zone. The first zone is written and/or erased in which one or more logical blocks have higher writing hit rate, and therefore the corresponding physical blocks in the first zone will be written more often. The next step is to find one or more free physical blocks in second zone. The physical blocks of the first zone are replaced by the physical blocks of the second zone if the number of write and/or erase to the first zone exceeds a threshold number. The replacement of physical blocks in the first zone by the physical blocks in the second zone may include the steps of copying data from the physical blocks in the first zone to the physical block in the second zone, and changing the pointer of logical blocks to point to the physical blocks in the second zone.

Abstract translation: 如下执行用于非易失性存储器的磨损均衡的方法。 首先，非易失性存储器被分成包括至少第一区域和第二区域的多个区域。 写入和/或擦除第一区域，其中一个或多个逻辑块具有较高的写入命中率，因此第一区域中相应的物理块将被更频繁地写入。 下一步是在第二个区域中找到一个或多个空闲的物理块。 如果第一区的写入次数和/或擦除次数超过阈值，则第一区的物理块被第二区的物理块替换。 通过第二区域中的物理块来替换第一区域中的物理块可以包括以下步骤：将数据从第一区域中的物理块复制到第二区域中的物理块，并将逻辑块的指针改变为点 到第二区的物理块。

公开(公告)号：US07499336B2

公开(公告)日：2009-03-03

申请号：US11748459

申请日：2007-05-14

Applicant: Yi-Ching Liu ,  I-Long Lee ,  Ming-Hung Chou ,  Fuja Shone

Inventor： Yi-Ching Liu ,  I-Long Lee ,  Ming-Hung Chou ,  Fuja Shone

IPC: G11C16/04

CPC classification number: G11C16/0458 ,  G11C16/12

Abstract: A programming method for programming stored bits in floating gates of a flash memory cell or selected flash memory cells of a flash memory array is utilized for applying SSI injection on said flash memory cell or said selected flash memory cells of a flash memory array is disclosed. Constant charges at the drain regions of said flash memory cell or said selected flash memory cells of the flash memory array is implemented with a capacitor and a related switch for suppressing variant injected-charges-related properties in applying the SSI injection. A constant biasing current, which may be implemented with a constant current source or a current mirror equipped with a constant current source, is applied on source regions of said flash memory cell or said selected flash memory cells of the flash memory array for enhancing the suppression of said variant biasing properties.

Abstract translation: 用于对闪速存储器单元的浮动栅极中的存储位进行编程的闪存存储器阵列的选定闪存单元的编程方法被用于在所述闪速存储器单元上施加SSI注入或者闪存阵列的所选闪存单元。 闪速存储器阵列的所述闪速存储器单元或所选闪存单元的漏极区域的恒定电荷用电容器和相关开关来实现，用于在应用SSI注入时抑制变型注入电荷相关的特性。 可以用恒定电流源或配备有恒定电流源的电流镜来实现的恒定偏置电流被施加在闪速存储器单元的所述闪速存储器单元的所述闪存单元的所述源区域上，或者用于增强抑制 的所述变体偏置属性。

公开(公告)号：US20060192244A1

公开(公告)日：2006-08-31

申请号：US11067659

申请日：2005-02-28

Applicant: Fuja Shone

Inventor： Fuja Shone

IPC: H01L29/788

CPC classification number: G11C16/0491 ,  G11C16/0458 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/7887

Abstract: A memory structure in a semiconductor substrate essentially comprises a first conductive line, two conductive blocks, two first dielectric spacers, a first dielectric layer, and a second conductive line. The first conductive line, e.g., a polysilicon line, is formed above the semiconductor substrate, and the two conductive blocks composed of polysilicon, for example, are formed at the two sides of the first conductive line and insulated from the first conductive line with the two first dielectric spacers. The first dielectric layer, such as an oxide/nitride/oxide (ONO) layer, is formed on the two second conductive blocks and above the first conductive line, and the second conductive line is formed on the first dielectric layer and is substantially perpendicular to the two doping regions. Accordingly, the stack of the conductive block, the first dielectric layer, and the second conductive line form a floating gate structure which can store charges. The first conductive line and conductive blocks function as a select gate and floating gates, respectively, whereas the doping regions and the second conductive line function as bit lines and a word line, respectively.

公开(公告)号：US20050148173A1

公开(公告)日：2005-07-07

申请号：US10750893

申请日：2004-01-05

Applicant: Fuja Shone

Inventor： Fuja Shone

IPC: H01L21/44 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/115

CPC classification number: H01L27/112 ,  H01L27/115 ,  H01L27/11556

Abstract: A method of manufacturing a non-volatile memory array having vertical field effect transistors is revealed. First, a semiconductor substrate having multiple trenches is provided, and then dopants are implanted into the semiconductor substrate to form first doping regions and second doping regions respectively serving as source and drain bit lines at different heights. Secondly, a gate dielectric including at least one nitride film, e.g., an oxide/nitride/oxide (ONO) layer, is formed onto the surface of the semiconductor substrate, and polysilicon plugs serving as gate electrodes are filled up the multiple trenches afterward. After that, a polysilicon layer and a tungsten silicide (WiSix) layer are sequentially deposited followed by masking and etching processes to form parallel polycide lines serving as word lines, and then an oxide layer is deposited therebetween and planarized for isolation.

Abstract translation: 揭示了制造具有垂直场效应晶体管的非易失性存储器阵列的方法。 首先，提供具有多个沟槽的半导体衬底，然后将掺杂剂注入到半导体衬底中，以形成分别用作不同高度的源极和漏极位线的第一掺杂区域和第二掺杂区域。 其次，在半导体衬底的表面上形成包括至少一个氮化物膜，例如氧化物/氮化物/氧化物（ONO）层的栅极电介质，并且用作栅电极的多晶硅栓随后填充多个沟槽。 之后，依次沉积多晶硅层和硅化钨（WiSix）层，然后进行掩模和蚀刻工艺，以形成平行的多余线，用作字线，然后在其间沉积氧化物层并进行平面化以进行隔离。

公开(公告)号：US07752383B2

公开(公告)日：2010-07-06

申请号：US11753572

申请日：2007-05-25

Applicant: Chuang Cheng ,  Ching-Chang Chen ,  Satoshi Sugawa ,  Wen-Lin Chang ,  Kai-Hsun Lin ,  Fuja Shone

Inventor： Chuang Cheng ,  Ching-Chang Chen ,  Satoshi Sugawa ,  Wen-Lin Chang ,  Kai-Hsun Lin ,  Fuja Shone

IPC: G06F12/00

CPC classification number: G06F13/4022

Abstract: A method and related system for programming connections between a NAND flash memory controller and a plurality of NAND flash memory modules includes the NAND flash memory controller generating a switch signal and a swap signal according to a condition of one of the plurality of NAND flash memory modules, a remap module selectively coupling the plurality of NAND flash memory modules to the NAND flash memory controller according to the switch signal, and a swap module selectively coupling the plurality of NAND flash memory modules to the NAND flash memory controller according to the swap signal.

Abstract translation: 一种用于在NAND闪速存储器控制器和多个NAND快闪存储器模块之间编程连接的方法和相关系统包括根据多个NAND快闪存储器模块之一的状态产生开关信号和交换信号的NAND闪存控制器 ，根据切换信号将多个NAND快闪存储器模块选择性地耦合到NAND闪速存储器控制器的重映射模块，以及根据交换信号有选择地将多个NAND快闪存储器模块耦合到NAND快闪存储器控制器的交换模块。