公开(公告)号：US20120096280A1

公开(公告)日：2012-04-19

申请号：US13336222

申请日：2011-12-23

Applicant: MING-SHEN LIN ,  CHIH-NAN YEN ,  FU-JA SHONE

Inventor： MING-SHEN LIN ,  CHIH-NAN YEN ,  FU-JA SHONE

IPC: H04L9/30

CPC classification number: H04L9/0897 ,  G06F21/79 ,  H04L9/3226

Abstract: A secured storage device uses a user key set by user to encrypt a primary key that is for encryption or decryption of user data, to produce a first encrypted data. In the secured storage device, neither the primary key nor the user key is stored, but the first encrypted data, and a secondary key and a second encrypted data produced from the secondary key encrypted with the user key for verifying the password inputted by user are stored. Therefore, even though a storage medium in the secured storage device is detached and read, the primary key and the user key cannot be obtained by a third party for reading out any encrypted user data from the secured storage device.

Abstract translation: 安全存储设备使用由用户设置的用户密钥来加密用于用户数据的加密或解密的主密钥，以产生第一加密数据。 在安全存储装置中，不存储主键和用户密钥，而是用用于验证用户输入的密码的用户密钥加密的第二加密数据和辅助密钥以及第二加密数据， 存储。 因此，即使分离和读取安全存储设备中的存储介质，也不能由第三方从安全存储设备读出加密的用户数据来获得主密钥和用户密钥。

公开(公告)号：US07911840B2

公开(公告)日：2011-03-22

申请号：US12318872

申请日：2009-01-12

Applicant: Hsin-Hsien Wu ,  Yu-Mao Kao ,  Yung-Li Ji ,  Chih-Nan Yen ,  Fu-Ja Shone

Inventor： Hsin-Hsien Wu ,  Yu-Mao Kao ,  Yung-Li Ji ,  Chih-Nan Yen ,  Fu-Ja Shone

IPC: G11C14/00

CPC classification number: G11C16/349

Abstract: A flash memory system includes a path selector to determine to write to a non-volatile memory, a volatile memory or both the non-volatile memory and the volatile memory when the flash memory system is to write data. A record is stored in the non-volatile memory which is updated the status of the non-volatile memory after each one or more writing operations. When the flash memory system is powered on after a power loss, it could be recovered to a command executed prior to the power loss or to any checkpoint prior to the power loss by using the record.

Abstract translation: 闪速存储器系统包括路径选择器，用于在闪存系统要写入数据时确定写入非易失性存储器，易失性存储器或非易失性存储器和易失性存储器。 一个记录被存储在非易失性存储器中，在每个一个或多个写入操作之后更新非易失性存储器的状态。 当闪存系统在掉电后上电时，可以将其恢复到在掉电前执行的命令，或者通过使用该记录恢复到断电前的任何检查点。

公开(公告)号：US20090198944A1

公开(公告)日：2009-08-06

申请号：US12026375

申请日：2008-02-05

Applicant: FUJA SHONE ,  CHIH NAN YEN ,  YUNG LI JI

Inventor： FUJA SHONE ,  CHIH NAN YEN ,  YUNG LI JI

IPC: G06F12/02

CPC classification number: G06F13/409

Abstract: An adaptive semiconductor memory device is used for being inserted into a host for storage. The semiconductor memory device comprises a non-volatile memory and a switch. The switch can be a logical switch or a physical switch that controls the semiconductor memory device to be in compliance with either a first specification version or a second specification version of the semiconductor memory device. The second specification version in comparison with the first specification version is used for higher capacity applications.

Abstract translation: 自适应半导体存储器件被用于插入主机以进行存储。 半导体存储器件包括非易失性存储器和开关。 开关可以是控制半导体存储器件符合半导体存储器件的第一规范版本或第二规范版本的逻辑开关或物理开关。 与第一个规范版本相比，第二个规范版本用于更高容量的应用。

公开(公告)号：US20090198919A1

公开(公告)日：2009-08-06

申请号：US12024149

申请日：2008-02-01

Applicant: Yung-Li Ji ,  Shih Chieh Tai ,  Chih Nan Yen ,  Fu-Ja Shone

Inventor： Yung-Li Ji ,  Shih Chieh Tai ,  Chih Nan Yen ,  Fu-Ja Shone

IPC: G06F12/00

CPC classification number: G06F3/0634 ,  G06F1/3221 ,  G06F1/3268 ,  G06F3/0625 ,  G06F3/0679 ,  Y02D10/154 ,  Y02D50/20

Abstract: A non-volatile memory device, and a method for accessing the non-volatile memory device are provided. The non-volatile memory device is connected to a host via a bus. The non-volatile memory device comprises an MCU. By independently processing the particular commands using only the auxiliary circuit, the MCU can cease to operate, thus saving power. By setting the bus into power saving mode when the non-volatile memory device is busy, the host and the non-volatile memory device would not communicate mutually, thus, saving power.

Abstract translation: 提供非易失性存储器件，以及用于访问非易失性存储器件的方法。 非易失性存储器件通过总线连接到主机。 非易失性存储器件包括MCU。 通过仅使用辅助电路独立处理特定命令，MCU可以停止工作，从而节省电力。 通过在非易失性存储器件忙时将总线设置为省电模式，主机和非易失性存储器件将不会相互通信，从而节省电力。

公开(公告)号：US08095724B2

公开(公告)日：2012-01-10

申请号：US12026400

申请日：2008-02-05

Applicant: Yung Li Ji ,  Chia Chen Chang ,  Chih Nan Yen ,  Fuja Shone

Inventor： Yung Li Ji ,  Chia Chen Chang ,  Chih Nan Yen ,  Fuja Shone

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC classification number: G06F12/0246 ,  C07D401/12 ,  G06F2212/7201 ,  G06F2212/7211

Abstract: A method of wear leveling for a non-volatile memory is disclosed. A non-volatile memory is divided into windows and gaps, with each gap between two adjacent windows. The windows comprise physical blocks mapped to logical addresses, and the gaps comprise physical blocks not mapped to logical addresses. The windows are shifted through the non-volatile memory in which the mapping to the physical blocks in the window to be shifted is changed to the physical blocks in the gap.

Abstract translation: 公开了一种用于非易失性存储器的磨损均衡的方法。 非易失性存储器分为窗口和间隙，两个相邻窗口之间的每个间隙。 窗口包括映射到逻辑地址的物理块，并且间隙包括未映射到逻辑地址的物理块。 窗口移动通过非易失性存储器，在该非易失性存储器中，将要移位的窗口中的物理块的映射改变为间隙中的物理块。

公开(公告)号：US20100088458A1

公开(公告)日：2010-04-08

申请号：US12245093

申请日：2008-10-03

Applicant: YU MAO KAO ,  YUNG LI JI ,  CHIH NAN YEN ,  FUJA SHONE

Inventor： YU MAO KAO ,  YUNG LI JI ,  CHIH NAN YEN ,  FUJA SHONE

IPC: G06F12/02 ,  G06F12/00 ,  G06F12/10

CPC classification number: G06F12/04 ,  G06F12/0246 ,  G06F2212/1016 ,  Y02D10/13

Abstract: An operation method of a memory includes the steps of calculating an offset of sequential write commands and the beginning of pages of a block of a non-volatile memory; shifting the block by the offset; and directly writing data from a host to the pages except the first and last pages of the block by the sequential write commands. In an embodiment, the pages are logical pages providing optimal writing efficiency and are determined before calculating the offset. The step of shifting the block by the offset is to increase corresponding logical block addresses (LBA) in the pages by the offset.

Abstract translation: 存储器的操作方法包括以下步骤：计算顺序写入命令的偏移和非易失性存储器的块的开头; 将块移动偏移; 并且通过顺序写入命令直接将数据从主机写入除块的第一页和最后一页之外的页面。 在一个实施例中，页面是提供最佳写入效率的逻辑页面，并且在计算偏移量之前确定。 通过偏移移位块的步骤是通过偏移增加页面中的对应逻辑块地址（LBA）。

公开(公告)号：US20090259819A1

公开(公告)日：2009-10-15

申请号：US12100136

申请日：2008-04-09

Applicant: YEN MING CHEN ,  SHIH CHIEH TAI ,  YUNG LI JI ,  CHIH NAN YEN ,  FUJA SHONE

Inventor： YEN MING CHEN ,  SHIH CHIEH TAI ,  YUNG LI JI ,  CHIH NAN YEN ,  FUJA SHONE

IPC: G06F12/02 ,  G06F13/00 ,  G06F12/00

CPC classification number: G06F13/4239

Abstract: A method of wear leveling for a non-volatile memory is performed as follows. First, the non-volatile memory is divided into a plurality of zones including at least a first zone and a second zone. The first zone is written and/or erased in which one or more logical blocks have higher writing hit rate, and therefore the corresponding physical blocks in the first zone will be written more often. The next step is to find one or more free physical blocks in second zone. The physical blocks of the first zone are replaced by the physical blocks of the second zone if the number of write and/or erase to the first zone exceeds a threshold number. The replacement of physical blocks in the first zone by the physical blocks in the second zone may include the steps of copying data from the physical blocks in the first zone to the physical block in the second zone, and changing the pointer of logical blocks to point to the physical blocks in the second zone.

Abstract translation: 如下执行用于非易失性存储器的磨损均衡的方法。 首先，非易失性存储器被分成包括至少第一区域和第二区域的多个区域。 写入和/或擦除第一区域，其中一个或多个逻辑块具有较高的写入命中率，因此第一区域中相应的物理块将被更频繁地写入。 下一步是在第二个区域中找到一个或多个空闲的物理块。 如果第一区的写入次数和/或擦除次数超过阈值，则第一区的物理块被第二区的物理块替换。 通过第二区域中的物理块来替换第一区域中的物理块可以包括以下步骤：将数据从第一区域中的物理块复制到第二区域中的物理块，并将逻辑块的指针改变为点 到第二区的物理块。

公开(公告)号：US09086456B2

公开(公告)日：2015-07-21

申请号：US13934239

申请日：2013-07-03

Applicant: Chih-Nan Yen ,  Chia-Wei Chang

Inventor： Chih-Nan Yen ,  Chia-Wei Chang

IPC: G01R31/3185 ,  G11C29/00 ,  G11C29/04

CPC classification number: G01R31/318536 ,  G06F11/1048 ,  G11C29/00 ,  G11C2029/0411

Abstract: A method for selecting the scrambling and descrambling data transmitted in a storage system containing ECC and scramble engines with a seed table is disclosed and the steps comprises: encoding a data sent from a HOST interface by an ECC encoding engine and transmitting the data to a LFSR scramble engine; scrambling the data by the LFSR scramble engine and transmitting to a storage device; creating a seed value and transmitting the seed value to a seed table by the LFSR scramble engine; receiving the seed value from the seed table and the scrambled data from the storage device by a LFSR descramble engine, and descrambling the scrambled data based on the seed value and transmitting to an ECC decoding engine; and decoding the descrambled data received from the LFSR descramble engine and then acquiring the original data sent from the HOST interface.

Abstract translation: 公开了一种用于选择在具有种子表的包含ECC和加扰引擎的存储系统中发送的加扰和解扰数据的方法，所述步骤包括：通过ECC编码引擎对从HOST接口发送的数据进行编码，并将数据发送到LFSR 争夺引擎 通过LFSR加扰引擎扰乱数据并发送到存储设备; 创建种子值并通过LFSR加扰引擎将种子值发送到种子表; 通过LFSR解扰引擎从种子表接收来自种子表的种子值和来自存储装置的加密数据，并且基于种子值对加扰数据进行解扰并发送到ECC解码引擎; 并对从LFSR解扰引擎接收的解扰数据进行解码，然后获取从HOST接口发送的原始数据。

公开(公告)号：US07839684B2

公开(公告)日：2010-11-23

申请号：US12382204

申请日：2009-03-11

Applicant: Yu-Mao Kao ,  Yung-Li Ji ,  Chih-Nan Yen ,  Fu-Ja Shone

Inventor： Yu-Mao Kao ,  Yung-Li Ji ,  Chih-Nan Yen ,  Fu-Ja Shone

IPC: G11C16/00

CPC classification number: G11C29/88 ,  G11C29/82

Abstract: The block groups of a multiple data channel flash memory storage device are detected for defective blocks. The block group containing any defective blocks is divided into subgroups, each of which contains only defective blocks or only good blocks. The subgroups containing only good blocks are selected to establish a new block group having the same amount of blocks as that of the original block groups.

Abstract translation: 针对缺陷块检测多数据通道闪存存储设备的块组。 包含任何缺陷块的块组被划分为子组，每个子组仅包含缺陷块或仅包含好的块。 选择仅包含好的块的子组以建立具有与原始块组相同的块数量的新块组。

公开(公告)号：US20100061150A1

公开(公告)日：2010-03-11

申请号：US12318872

申请日：2009-01-12

Applicant: Hsin-Hsien Wu ,  Yu-Mao Kao ,  Yung-Li Ji ,  Chih-Nan Yen ,  Fu-Ja Shone

Inventor： Hsin-Hsien Wu ,  Yu-Mao Kao ,  Yung-Li Ji ,  Chih-Nan Yen ,  Fu-Ja Shone

IPC: G11C16/04 ,  G11C16/06 ,  G11C5/14

CPC classification number: G11C16/349

Abstract: A flash memory system includes a path selector to determine to write to a non-volatile memory, a volatile memory or both the non-volatile memory and the volatile memory when the flash memory system is to write data. A record is stored in the non-volatile memory which is updated the status of the non-volatile memory after each one or more writing operations. When the flash memory system is powered on after a power loss, it could be recovered to a command executed prior to the power loss or to any checkpoint prior to the power loss by using the record.

Abstract translation: 闪速存储器系统包括路径选择器，用于在闪存系统要写入数据时确定写入非易失性存储器，易失性存储器或非易失性存储器和易失性存储器。 一个记录被存储在非易失性存储器中，在每个一个或多个写入操作之后更新非易失性存储器的状态。 当闪存系统在掉电后上电时，可以将其恢复到在掉电前执行的命令，或者通过使用该记录恢复到断电前的任何检查点。