公开(公告)号：US20230411470A1

公开(公告)日：2023-12-21

申请号：US18320309

申请日：2023-05-19

申请人： FORCE MOS TECHNOLOGY CO., LTD.

发明人： Kao-Way TU ,  Yuan-Shun CHANG ,  Po-An TSAI ,  Huan-Chung WENG

IPC分类号： H01L29/417 ,  H01L29/78 ,  H01L29/66

CPC分类号： H01L29/41741 ,  H01L29/66734 ,  H01L29/66727 ,  H01L29/7813

摘要： A trench-gate field effect transistor includes a plurality of trenches, a plurality of gate electrode units, and a plurality of source electrode units. Each of the trenches has a first trench region, a second trench region having a width less than that of the first trench region, and a neck trench region extending between the first trench region and the second trench region. Each of the gate electrode units includes a pair of first gate electrode portions disposed in the first trench region, a pair of second gate electrode portions disposed in the neck trench region, and a third gate electrode portion disposed in the second trench region. Each of the source electrode units includes a first source electrode portion disposed between a pair of the first gate electrode portions, and a second source electrode portion connected to the first source electrode portion.

公开(公告)号：US09293527B1

公开(公告)日：2016-03-22

申请号：US14644361

申请日：2015-03-11

申请人： Force Mos Technology Co., Ltd.

发明人： Fu-Yuan Hsieh

IPC分类号： H01L29/06 ,  H01L29/78 ,  H01L29/49 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45

CPC分类号： H01L29/0634 ,  H01L21/26586 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/45 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827

摘要： A super-junction trench MOSFET is disclosed by applying a first doped column region of first conductivity type between a pair of second doped column regions of second conductivity type adjacent to sidewalls of a pair of deep trenches with buried voids in each unit cell for super-junction. A buffer poly-silicon layer is deposited above the buried void for stress release to prevent wafer crack and silicon defects.

摘要翻译： 公开了一种超结沟槽MOSFET，其通过在第一导电类型的一对第二掺杂列区域之间施加与第一导电类型的第二掺杂列区域相邻的一对深沟槽的侧壁，在每个单元电池中具有掩埋空隙， 交界处 缓冲多晶硅层沉积在掩埋空间之上，用于释放应力以防止晶片裂纹和硅缺陷。

公开(公告)号：US20150037954A1

公开(公告)日：2015-02-05

申请号：US14516704

申请日：2014-10-17

申请人： Force Mos Technology Co., Ltd.

发明人： FU-YUAN HSIEH

IPC分类号： H01L29/66

CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/41766 ,  H01L29/423 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

摘要： A super-junction trench MOSFET with a short termination area is disclosed, wherein the short termination area comprising a charge balance region and a channel stop region formed near a top surface of an epitaxial layer with a trenched termination contact penetrating therethrough.

摘要翻译： 公开了具有短端接区域的超结沟槽MOSFET，其中短终端区域包括电荷平衡区域和在外延层的顶表面附近形成的沟槽停止区域，其中沟槽端接触头贯穿其中。

公开(公告)号：US20140291753A1

公开(公告)日：2014-10-02

申请号：US13851185

申请日：2013-03-27

申请人： FORCE MOS TECHNOLOGY CO., LTD.

发明人： FU-YUAN HSIEH

IPC分类号： H01L29/66 ,  H01L29/78

CPC分类号： H01L29/7827 ,  H01L29/086 ,  H01L29/0869 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813

摘要： A trench MOSFET structure having self-aligned features for mask saving and on-resistance reduction is disclosed, wherein the source region is formed by performing source Ion Implantation through contact opening of a contact interlayer, and further source diffusion. A dielectric sidewall spacer is formed on sidewalls of the contact interlayer in the contact open areas to define trenched source-body contacts for on-resistance reduction and avalanche capability improvement.

摘要翻译： 公开了具有用于掩模保护和导通电阻降低的自对准特征的沟槽MOSFET结构，其中通过通过接触中间层的接触开口进行源离子注入和进一步的源极扩散来形成源极区域。 在接触开放区域中的接触中间层的侧壁上形成电介质侧壁间隔物，以限定用于导通电阻降低和雪崩能力改进的沟槽源体接触。

公开(公告)号：US20130299901A1

公开(公告)日：2013-11-14

申请号：US13949336

申请日：2013-07-24

申请人： Force Mos Technology Co., Ltd.

发明人： FU-YUAN HSIEH

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L29/7813 ,  H01L21/823437 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7811

摘要： A trench MOSFET comprising a plurality of trenched gates surrounded by source regions encompassed in body regions in active area. A plurality of trenched source-body contact structure penetrating through the source regions and extending into the body regions, are filled with tungsten plugs padded with a Ti layer, a first and a second TiN layer, wherein the second TiN layer is deposited after Ti silicide formation to avoid W spiking occurrence.

摘要翻译： 一种沟槽MOSFET，包括被包围在有源区域的主体区域中的源极区域包围的多个沟槽栅极。 穿过源极区域并延伸到体区的多个沟槽的源体接触结构填充有填充有Ti层，第一和第二TiN层的钨插塞，其中第二TiN层在Ti硅化物之后沉积 形成避免W尖峰发生。

公开(公告)号：US20200251468A1

公开(公告)日：2020-08-06

申请号：US16600738

申请日：2019-10-14

申请人： Force MOS Technology Co., Ltd.

发明人： Kao-Way Tu ,  Yuan-Shun CHANG

IPC分类号： H01L27/088 ,  H01L29/417 ,  H01L29/423 ,  H01L23/535

摘要： A metal-oxide-semiconductor (MOS) device comprising a heavily doped substrate, epitaxialan layer, an open, a plurality of MOS units, and a metal pattern layer is provided. The epitaxial layer is formed on the heavily doped substrate. The open is defined in the epitaxial layer to expose the heavily doped substrate. The MOS units are formed on the epitaxial layer. The metal pattern layer comprises a source metal pattern, a gate metal pattern, and a drain metal pattern. The source metal pattern and the gate metal pattern are formed on the epitaxial layer. The drain metal pattern fills in the open and is extended from the heavily doped substrate upward to above the epitaxial layer.

公开(公告)号：US20200105890A1

公开(公告)日：2020-04-02

申请号：US16244395

申请日：2019-01-10

申请人： Force MOS Technology Co., Ltd.

发明人： Kao-Way Tu ,  Po-An Tsai ,  Huan-Chung Weng

IPC分类号： H01L29/423 ,  H01L29/40 ,  H01L29/78

摘要： A fabricating method of a shielded gate MOSFET is provided, including steps of: forming a semiconductor substrate having a trench; forming a sacrifice oxide layer in the trench, the sacrifice oxide layer covering a side wall of the trench; forming a source polycrystalline silicon region in the trench; forming an insulation oxide layer above the source polycrystalline silicon region to have the source polycrystalline silicon region fully enclosed by the sacrifice oxide layer and the insulation oxide layer; depositing polycrystalline silicon into the trench and carrying out a back etching to control a thickness of the insulation oxide layer above the source polycrystalline silicon region; forming a gate oxide layer in the trench, the gate oxide layer covering the side wall of the trench; forming a gate polycrystalline silicon region in the trench; and forming a body layer and a heavily doped region around the trench in an ion implantation manner.

公开(公告)号：US20170317207A1

公开(公告)日：2017-11-02

申请号：US15141907

申请日：2016-04-29

申请人： Force Mos Technology Co., Ltd.

发明人： Fu-Yuan HSIEH

IPC分类号： H01L29/78 ,  H01L21/265 ,  H01L29/423 ,  H01L29/417 ,  H01L29/40 ,  H01L29/36 ,  H01L29/167 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L21/3213 ,  H01L21/321 ,  H01L21/3205 ,  H01L21/308 ,  H01L21/266 ,  H01L29/66

摘要： A trench MOSFET with closed cell layout having shielded gate is disclosed, wherein closed gate trenches surrounding a deep trench in each unit cell and the shielded gate disposed in the deep trench. Trenched source-body contacts are formed between the closed gate trenches and the deep trench. The deep trench has square, rectangular, circle or hexagon shape.

公开(公告)号：US20170278837A1

公开(公告)日：2017-09-28

申请号：US15080639

申请日：2016-03-25

申请人： Force Mos Technology Co., Ltd

发明人： Fu-Yuan HSIEH

IPC分类号： H01L27/02 ,  H01L29/66 ,  H01L23/535 ,  H01L23/532 ,  H01L29/40 ,  H01L29/78

CPC分类号： H01L27/0255 ,  H01L23/53266 ,  H01L23/535 ,  H01L29/407 ,  H01L29/66734 ,  H01L29/7805 ,  H01L29/7808 ,  H01L29/7813

摘要： A semiconductor power device having shielded gate structure in an active area and having ESD clamp diode with two poly-silicon layer process is disclosed, wherein: the shielded gate structure comprises a first poly-silicon layer to serve as a shielded electrode and a second poly-silicon layer to serve as a gate electrode, and the ESD clamp diode formed between two protruding electrodes is also formed by the first poly-silicon layer. A mask specially used to define the ESD clamp diode portion is saved.

公开(公告)号：US09412810B2

公开(公告)日：2016-08-09

申请号：US14592223

申请日：2015-01-08

申请人： Force Mos Technology Co., Ltd.

发明人： Fu-Yuan Hsieh

IPC分类号： H01L29/06 ,  H01L29/78 ,  H01L29/423 ,  H01L29/10 ,  H01L29/49 ,  H01L29/417 ,  H01L23/535

CPC分类号： H01L29/0634 ,  H01L21/26586 ,  H01L23/535 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4916 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

摘要： A super-junction trench MOSFET with closed cell layout having shielded gate is disclosed, wherein closed gate trenches surrounding a deep trench in each unit cell and the shielded gate disposed in the deep trench. Trenched source-body contacts are at least formed between the closed gate trenches and the deep trench. The deep trench has square, rectangular, circle or hexagon shape.

摘要翻译： 公开了具有屏蔽栅极的具有闭孔布局的超结沟槽MOSFET，其中围绕每个单元电池中的深沟槽的封闭栅极沟槽和设置在深沟槽中的屏蔽栅极。 至少在闭合栅极沟槽和深沟槽之间形成有沟槽的源体接触。 深沟有方形，矩形，圆形或六边形。