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    Nonvolatile memory device and method for fabricating the same
    1.
    发明授权
    Nonvolatile memory device and method for fabricating the same 有权
    非易失性存储器件及其制造方法

    公开(公告)号：US08928059B2

    公开(公告)日：2015-01-06

    申请号：US13605213

    申请日：2012-09-06

    Applicant: Sung-Jin Whang ,  Dong-Sun Sheen ,  Seung-Ho Pyi ,  Min-Soo Kim

    Inventor： Sung-Jin Whang ,  Dong-Sun Sheen ,  Seung-Ho Pyi ,  Min-Soo Kim

    IPC: H01L29/788

    CPC classification number: H01L27/11556 ,  H01L21/28273 ,  H01L29/66825 ,  H01L29/7889

    Abstract: A nonvolatile memory device includes a substrate; a channel layer projecting from a surface of the substrate, in a direction perpendicular to the surface; a tunnel dielectric layer surrounding the channel layer; a plurality of interlayer dielectric layers and a plurality of control gate electrodes alternately formed along the channel layer; floating gate electrodes interposed between the tunnel dielectric layer and the plurality of control gate electrodes, the floating gate electrodes comprising a metal-semiconductor compound; and a charge blocking layer interposed between each of the plurality of control gate electrodes and each of the plurality of floating gate electrodes.

    Abstract translation: 非易失性存储器件包括：衬底; 从所述基板的表面在垂直于所述表面的方向上突出的沟道层; 围绕所述沟道层的隧道介电层; 多个层间电介质层和沿沟道层交替形成的多个控制栅电极; 插入在隧道介电层和多个控制栅电极之间的浮置栅电极，浮置栅电极包括金属 - 半导体化合物; 以及插入在所述多个控制栅极电极和所述多个浮栅电极中的每一个之间的电荷阻挡层。

    Nonvolatile memory device and method for fabricating the same
    2.
    发明授权
    Nonvolatile memory device and method for fabricating the same 有权
    非易失性存储器件及其制造方法

    公开(公告)号：US08860119B2

    公开(公告)日：2014-10-14

    申请号：US13604073

    申请日：2012-09-05

    Applicant: Min-Soo Kim ,  Dong-Sun Sheen ,  Seung-Ho Pyi ,  Sung-Jin Whang

    Inventor： Min-Soo Kim ,  Dong-Sun Sheen ,  Seung-Ho Pyi ,  Sung-Jin Whang

    IPC: H01L29/78 ,  H01L21/283

    CPC classification number: H01L27/11582

    Abstract: A nonvolatile memory device includes a substrate including a surface, a channel layer formed on the surface of the substrate, which protrudes perpendicularly from the surface, and a plurality of interlayer dielectric layers and a plurality of gate electrode layers alternately stacked along the channel layer, wherein the plurality of gate electrode layers protrude from the plurality of interlayer dielectric layers.

    Abstract translation: 非易失性存储器件包括：衬底，其包括表面，形成在所述衬底的表面上的从所述表面垂直突出的沟道层，以及沿所述沟道层交替堆叠的多个层间电介质层和多个栅极电极层， 其中所述多个栅极电极层从所述多个层间电介质层突出。

    Method of forming isolation structure of semiconductor device for preventing excessive loss during recess gate formation
    5.
    发明授权
    Method of forming isolation structure of semiconductor device for preventing excessive loss during recess gate formation 失效
    形成半导体器件的隔离结构的方法，用于防止在凹陷栅极形成期间的过度损耗

    公开(公告)号：US07687371B2

    公开(公告)日：2010-03-30

    申请号：US12243133

    申请日：2008-10-01

    Applicant: Dong Sun Sheen ,  Seok Pyo Song ,  Sang Tae Ahn ,  Hyeon Ju An

    Inventor： Dong Sun Sheen ,  Seok Pyo Song ,  Sang Tae Ahn ,  Hyeon Ju An

    IPC: H01L21/76

    CPC classification number: H01L21/76224

    Abstract: An isolation structure of a semiconductor device is formed by forming a hard mask layer on a semiconductor substrate having active and field regions to expose the field region. A trench is defined by etching the exposed field region of the semiconductor substrate using the hard mask as an etch mask. An SOG layer is formed in the trench partially filling the trench. An amorphous aluminum oxide layer is formed on the resultant substrate including the SOG layer. An HDP layer is formed on the amorphous aluminum oxide layer to completely fill the trench. The HDP layer and the amorphous aluminum oxide layer are subjected to CMP to expose the hard mask. The hard mask and portions of the amorphous aluminum oxide layer that are formed on the HDP layer are removed. The amorphous aluminum oxide layer is crystallized.

    Abstract translation: 半导体器件的隔离结构通过在具有活性和场区域的半导体衬底上形成硬掩模层以暴露场区而形成。 通过使用硬掩模作为蚀刻掩模蚀刻半导体衬底的曝光场区来限定沟槽。 SOG层形成在部分填充沟槽的沟槽中。 在包含SOG层的所得基板上形成无定形氧化铝层。 在无定形氧化铝层上形成HDP层以完全填充沟槽。 对HDP层和无定形氧化铝层进行CMP以暴露硬掩模。 去除形成在HDP层上的硬掩模和无定形氧化铝层的部分。 无定形氧化铝层结晶。

    Method for manufacturing fin transistor that prevents etching loss of a spin-on-glass insulation layer
    6.
    发明授权
    Method for manufacturing fin transistor that prevents etching loss of a spin-on-glass insulation layer 失效
    用于制造防止玻璃化玻璃绝缘层的蚀刻损失的鳍式晶体管的方法

    公开(公告)号：US07687355B2

    公开(公告)日：2010-03-30

    申请号：US11965835

    申请日：2007-12-28

    Applicant: Dong Sun Sheen ,  Seok Pyo Song ,  Young Ho Lee

    Inventor： Dong Sun Sheen ,  Seok Pyo Song ,  Young Ho Lee

    IPC: H01L21/336

    CPC classification number: H01L29/66795 ,  H01L29/7851

    Abstract: A method for manufacturing a fin transistor includes forming a trench by etching a semiconductor substrate. A flowable insulation layer is filled in the trench to form a field insulation layer defining an active region. The portion of the flowable insulation layer coming into contact with a gate forming region is etched so as to protrude the gate forming region in the active region. A protective layer over the semiconductor substrate is formed to fill the portion of the etched flowable insulation layer. The portion of the protective layer formed over the active region is removed to expose the active region of the semiconductor substrate. The exposed active region of the semiconductor substrate is cleaned. The protective layer remaining on the portion of the etched flowable insulation layer is removed. Gates are formed over the protruded gate forming regions in the active region.

    Abstract translation: 一种制造鳍式晶体管的方法包括：通过蚀刻半导体衬底形成沟槽。 可流动的绝缘层填充在沟槽中以形成限定有源区的场绝缘层。 与栅极形成区域接触的可流动绝缘层的部分被蚀刻以便在有源区域中突出栅极形成区域。 形成半导体衬底上方的保护层以填充该可蚀刻的可流动绝缘层的部分。 在有源区上形成的保护层的部分被去除以暴露半导体衬底的有源区。 清洁半导体衬底的暴露的有源区。 残留在可蚀刻的可流动绝缘层的部分上的保护层被去除。 在活性区域中的突出的栅极形成区域上形成栅极。

    Method of Fabricating Non-Volatile Memory Device
    7.
    发明申请
    Method of Fabricating Non-Volatile Memory Device 失效
    制造非易失性存储器件的方法

    公开(公告)号：US20090170283A1

    公开(公告)日：2009-07-02

    申请号：US12164879

    申请日：2008-06-30

    Applicant: Dong Sun Sheen ,  Seok Pyo Song

    Inventor： Dong Sun Sheen ,  Seok Pyo Song

    IPC: H01L21/762 ,  H01L21/28

    CPC classification number: H01L21/76232 ,  H01L27/11521

    Abstract: A method of fabricating a non-volatile memory device, A tunnel insulating layer, a floating gate, and a pad nitride layer is formed on a semiconductor substrate. A isolation region of the semiconductor substrate is formed by etching to a predetermined depth, and a liner insulating layer is formed on an entire surface of the resulting trench for device isolation. A filling insulation layer is formed on the liner insulating layer to fill the trench and a first etching process is performed on the filling insulation layer and the liner insulating layer. The surface of semiconductor is recessed by performing a second etching process on the filling insulation layer. A capping layer is formed on an entire surface of the result formed by the second etching process. The device isolation layer of a concave shape is formed by performing an etching process on the capping layer.

    Abstract translation: 一种制造非易失性存储器件的方法，在半导体衬底上形成隧道绝缘层，浮栅和衬垫氮化物层。 通过蚀刻到预定深度形成半导体衬底的隔离区域，并且在所形成的用于器件隔离的沟槽的整个表面上形成衬垫绝缘层。 填充绝缘层形成在衬垫绝缘层上以填充沟槽，并且在填充绝缘层和衬里绝缘层上执行第一蚀刻工艺。 通过对填充绝缘层进行第二蚀刻工艺来使半导体的表面凹陷。 在通过第二蚀刻工艺形成的结果的整个表面上形成覆盖层。 通过对封盖层进行蚀刻工艺来形成凹形的器件隔离层。

    Method for Forming Gate of Non-Volatile Memory Device
    8.
    发明申请
    Method for Forming Gate of Non-Volatile Memory Device 审中-公开
    非易失性存储器件门形成方法

    公开(公告)号：US20090163013A1

    公开(公告)日：2009-06-25

    申请号：US12131558

    申请日：2008-06-02

    Applicant: Seok Pyo Song ,  Dong Sun Sheen ,  Seung Ho Pyi ,  Ki Seon Park ,  Sun Hwan Hwang ,  Mi Ri Lee ,  Gil Jae Park

    Inventor： Seok Pyo Song ,  Dong Sun Sheen ,  Seung Ho Pyi ,  Ki Seon Park ,  Sun Hwan Hwang ,  Mi Ri Lee ,  Gil Jae Park

    IPC: H01L21/28

    CPC classification number: H01L27/11568 ,  H01L27/115 ,  H01L27/11521

    Abstract: Provided is a method for forming a gate of a non-volatile memory device. A tunneling layer, a charge trapping layer, a blocking layer, and a control gate layer are formed on a semiconductor substrate. A hard mask is formed on the control gate layer. The hard mask defines a region on which a gate is formed. A gate pattern is formed by etching the control gate layer, the blocking layer, the charge trapping layer, and the tunneling layer. A damage compensation layer on a side of the gate pattern is formed using ultra low pressure plasma of a pressure range from approximately 1 mT to approximately 100 mT.

    Abstract translation: 提供了一种用于形成非易失性存储器件的栅极的方法。 在半导体衬底上形成隧道层，电荷俘获层，阻挡层和控制栅极层。 在控制栅极层上形成硬掩膜。 硬掩模限定形成栅极的区域。 通过蚀刻控制栅极层，阻挡层，电荷俘获层和隧道层形成栅极图案。 使用压力范围为约1mT至约100mT的超低压等离子体形成栅极图案侧的损伤补偿层。

    Non-volatile memory device and method for fabricating the same
    10.
    发明授权
    Non-volatile memory device and method for fabricating the same 有权
    非易失性存储器件及其制造方法

    公开(公告)号：US08928063B2

    公开(公告)日：2015-01-06

    申请号：US13618182

    申请日：2012-09-14

    Applicant: Min-Soo Kim ,  Dong-Sun Sheen ,  Seung-Ho Pyi ,  Sung-Jin Whang

    Inventor： Min-Soo Kim ,  Dong-Sun Sheen ,  Seung-Ho Pyi ,  Sung-Jin Whang

    IPC: H01L29/792 ,  H01L21/20

    CPC classification number: H01L21/28282 ,  H01L27/11582 ,  H01L29/66666 ,  H01L29/66833 ,  H01L29/792

    Abstract: A non-volatile memory device includes a channel layer vertically extending from a substrate, a plurality of inter-layer dielectric layers and a plurality of gate electrodes that are alternately stacked along the channel layer, and an air gap interposed between the channel layer and each of the plurality of gate electrodes. The non-volatile memory device may improve erase operation characteristics by suppressing back tunneling of electrons by substituting a charge blocking layer interposed between a gate electrode and a charge storage layer with an air gap, and a method for fabricating the non-volatile memory device.

    Abstract translation: 非易失性存储器件包括从衬底垂直延伸的沟道层，沿着沟道层交替层叠的多个层间电介质层和多个栅极电极，以及插入在沟道层和每个沟道层之间的气隙 的多个栅电极。 非易失性存储器件可以通过用插入位于栅电极和具有气隙的电荷存储层之间的电荷阻挡层来抑制电子的反向隧道而提高擦除操作特性，以及制造非易失性存储器件的方法。

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