公开(公告)号：US07687362B2

公开(公告)日：2010-03-30

申请号：US11941194

申请日：2007-11-16

Applicant: Seok Pyo Song ,  Dong Sun Sheen ,  Young Ho Lee

Inventor： Seok Pyo Song ,  Dong Sun Sheen ,  Young Ho Lee

IPC: H01L29/78

CPC classification number: H01L29/66621 ,  H01L29/4236

Abstract: A semiconductor device includes a semiconductor substrate having an active region including a channel portion. An isolation layer is formed in the semiconductor substrate to define the active region, and a gate is formed over the channel portion in the active region. The active region of the semiconductor substrate is etched to such that the entire active region is below an upper surface of the isolation layer. A U-shaped groove is formed in the channel portion of the active region, except the edges in a direction of the channel width thereof, in order to increase the channel width. In the semiconductor device, there is an increase in channel length and channel width leading to a reduction in leakage current and on increase in operation current.

Abstract translation: 半导体器件包括具有包括沟道部分的有源区的半导体衬底。 在半导体衬底中形成隔离层以限定有源区，并且在有源区中的沟道部分之上形成栅极。 蚀刻半导体衬底的有源区，使得整个有源区在隔离层的上表面下方。 为了增加通道宽度，在活性区域的通道部分中形成U形槽，除了其通道宽度方向上的边缘之外。 在半导体器件中，通道长度和通道宽度增加，导致漏电流的减小和工作电流的增加。

公开(公告)号：US07563654B2

公开(公告)日：2009-07-21

申请号：US11647759

申请日：2006-12-29

Applicant: Dong Sun Sheen ,  Seok Pyo Song ,  Sang Tae Ahn ,  Hyeon Ju An ,  Hyun Chul Sohn

Inventor： Dong Sun Sheen ,  Seok Pyo Song ,  Sang Tae Ahn ,  Hyeon Ju An ,  Hyun Chul Sohn

IPC: H01L21/335

CPC classification number: H01L27/0886 ,  H01L27/1214

Abstract: A method for manufacturing a semiconductor device is disclosed. The method includes the steps of defining a trench into a field region of a semiconductor substrate having an active region and the field region; partially filing the trench with a flowable insulation layer; completely filling the trench with an isolation structure by depositing a close-packed insulation layer on the flowable insulation layer in the trench; etching through a portion of the close-packed insulation layer and etching into a partial thickness of the flowable insulation layer of the insulation structure to expose a portion of the active region; cleaning the resultant substrate having the active region relatively projected; forming spacers on etched portions of the flowable insulation layer where bowing occurs during the cleaning step; and forming gates on the active region and the insulation structure to border the exposed portion of the active region.

Abstract translation: 公开了一种制造半导体器件的方法。 该方法包括以下步骤：将沟槽定义为具有有源区域和场区域的半导体衬底的场区域; 用可流动的绝缘层部分地填充沟槽; 通过在沟槽中的可流动绝缘层上沉积紧密堆积的绝缘层，通过隔离结构完全填充沟槽; 蚀刻通过所述紧密封装绝缘层的一部分并蚀刻成所述绝缘结构的可流动绝缘层的部分厚度以暴露所述有源区的一部分; 清洁具有相对投影的活性区域的所得基材; 在清洁步骤中发生弯曲的可流动绝缘层的蚀刻部分上形成间隔物; 以及在所述有源区和所述绝缘结构上形成栅极以与所述有源区的所述暴露部分相接触。

公开(公告)号：US08178921B2

公开(公告)日：2012-05-15

申请号：US12638233

申请日：2009-12-15

Applicant: Dong Sun Sheen ,  Sang Tae Ahn ,  Seok Pyo Song ,  Hyeon Ju An

Inventor： Dong Sun Sheen ,  Sang Tae Ahn ,  Seok Pyo Song ,  Hyeon Ju An

IPC: H01L29/78

CPC classification number: H01L29/78609 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device includes a semiconductor substrate having an active region which includes a gate forming zone and an isolation region; an isolation layer formed in the isolation region of the semiconductor substrate to expose side surfaces of a portion of the active region including the gate forming zone, such that the portion of the active region including the gate forming zone constitutes a fin pattern; a silicon epitaxial layer formed on the active region including the fin pattern; and a gate formed to cover the fin pattern on which the silicon epitaxial layer is formed.

Abstract translation: 半导体器件包括具有包括栅极形成区和隔离区的有源区的半导体衬底; 隔离层，其形成在所述半导体衬底的隔离区域中，以暴露包括所述栅极形成区的有源区的一部分的侧表面，使得包括所述栅极形成区的有源区的所述部分构成鳍状图案; 形成在包括鳍状图案的有源区上的硅外延层; 以及形成为覆盖其上形成有硅外延层的鳍图案的栅极。

公开(公告)号：US07795086B2

公开(公告)日：2010-09-14

申请号：US12346011

申请日：2008-12-30

Applicant: Young Jin Lee ,  Dong Sun Sheen ,  Seok Pyo Song ,  Mi Ri Lee ,  Chi Ho Kim ,  Gil Jae Park ,  Bo Min Seo

Inventor： Young Jin Lee ,  Dong Sun Sheen ,  Seok Pyo Song ,  Mi Ri Lee ,  Chi Ho Kim ,  Gil Jae Park ,  Bo Min Seo

IPC: H01L21/8238

CPC classification number: H01L21/823814 ,  H01L21/823425 ,  H01L21/823835

Abstract: A method for manufacturing a semiconductor device using a salicide process, which includes forming a gate dielectric layer over a silicon substrate including a PMOS region and an NMOS region; forming a first silicon pattern in the NMOS region and a second silicon pattern in the PMOS region; forming a first metal layer that is in contact with the first silicon pattern and the exposed first portion of the silicon substrate; and forming a first gate, a first junction, a second gate, and a second junction by performing a heat treatment to silicify the respective first and second silicon patterns and the silicon substrate.

Abstract translation: 一种使用自对准硅化物工艺制造半导体器件的方法，包括在包括PMOS区域和NMOS区域的硅衬底上形成栅极电介质层; 在所述NMOS区域中形成第一硅图案和在所述PMOS区域中形成第二硅图案; 形成与所述第一硅图案和所述暴露的所述硅衬底的第一部分接触的第一金属层; 以及通过进行热处理以使相应的第一和第二硅图案和硅衬底硅化而形成第一栅极，第一结，第二栅极和第二结。

公开(公告)号：US20090029523A1

公开(公告)日：2009-01-29

申请号：US12179448

申请日：2008-07-24

Applicant: Ji Hyun Seo ,  Seok Pyo Song ,  Dong Sun Sheen

Inventor： Ji Hyun Seo ,  Seok Pyo Song ,  Dong Sun Sheen

IPC: H01L21/762

CPC classification number: H01L21/3081 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76232 ,  H01L27/11521

Abstract: The invention relates to a method of fabricating flash memory device. In accordance with an aspect of the invention, the method includes forming a gate insulating layer, a first conductive layer, and an isolation mask over a semiconductor substrate. The isolation mask is patterned to expose regions in which an isolation layer will be formed. The first conductive layer, the gate insulating layer, and the semiconductor substrate are etched using the patterned isolation mask to form trenches. A liner oxide layer is formed on the resulting structure including the trenches. The trenches in which the liner oxide layer is formed are filled with an insulating layer. A planarizing process and a cleaning process are carried out such that wing spacers covering the gate insulating layer are formed at top edge portions of the isolation layer, thereby forming the isolation layer.

Abstract translation: 本发明涉及一种制造闪速存储器件的方法。 根据本发明的一个方面，所述方法包括在半导体衬底上形成栅绝缘层，第一导电层和隔离掩模。 隔离掩模被图案化以暴露其中将形成隔离层的区域。 使用图案化隔离掩模蚀刻第一导电层，栅极绝缘层和半导体衬底，以形成沟槽。 在包括沟槽的所得结构上形成衬里氧化物层。 形成衬垫氧化物层的沟槽填充有绝缘层。 执行平面化处理和清洁处理，使得覆盖栅绝缘层的翼间隔件形成在隔离层的顶部边缘部分，从而形成隔离层。

公开(公告)号：US20090186456A1

公开(公告)日：2009-07-23

申请号：US12346011

申请日：2008-12-30

Applicant: Young Jin Lee ,  Dong Sun Sheen ,  Seok Pyo Song ,  Mi Ri Lee ,  Chi Ho Kim ,  Gil Jae Park ,  Bo Min Seo

Inventor： Young Jin Lee ,  Dong Sun Sheen ,  Seok Pyo Song ,  Mi Ri Lee ,  Chi Ho Kim ,  Gil Jae Park ,  Bo Min Seo

IPC: H01L21/8238

CPC classification number: H01L21/823814 ,  H01L21/823425 ,  H01L21/823835

Abstract: A method for manufacturing a semiconductor device using a salicide process, which includes forming a gate dielectric layer over a silicon substrate including a PMOS region and an NMOS region; forming a first silicon pattern in the NMOS region and a second silicon pattern in the PMOS region; forming a first metal layer that is in contact with the first silicon pattern and the exposed first portion of the silicon substrate; and forming a first gate, a first junction, a second gate, and a second junction by performing a heat treatment to silicify the respective first and second silicon patterns and the silicon substrate.

Abstract translation: 一种使用自对准硅化物工艺制造半导体器件的方法，包括在包括PMOS区域和NMOS区域的硅衬底上形成栅极电介质层; 在所述NMOS区域中形成第一硅图案和在所述PMOS区域中形成第二硅图案; 形成与所述第一硅图案和所述暴露的所述硅衬底的第一部分接触的第一金属层; 以及通过进行热处理以使相应的第一和第二硅图案和硅衬底硅化而形成第一栅极，第一结，第二栅极和第二结。

公开(公告)号：US20070281454A1

公开(公告)日：2007-12-06

申请号：US11647759

申请日：2006-12-29

Applicant: Dong Sun Sheen ,  Seok Pyo Song ,  Sang Tae Ahn ,  Hyeon Ju An ,  Hyun Chul Sohn

Inventor： Dong Sun Sheen ,  Seok Pyo Song ,  Sang Tae Ahn ,  Hyeon Ju An ,  Hyun Chul Sohn

IPC: H01L21/3205

CPC classification number: H01L27/0886 ,  H01L27/1214

Abstract: A method for manufacturing a semiconductor device is disclosed. The method includes the steps of defining a trench into a field region of a semiconductor substrate having an active region and the field region; partially filing the trench with a flowable insulation layer; completely filling the trench with an isolation structure by depositing a close-packed insulation layer on the flowable insulation layer in the trench; etching through a portion of the close-packed insulation layer and etching into a partial thickness of the flowable insulation layer of the insulation structure to expose a portion of the active region; cleaning the resultant substrate having the active region relatively projected; forming spacers on etched portions of the flowable insulation layer where bowing occurs during the cleaning step; and forming gates on the active region and the insulation structure to border the exposed portion of the active region.

Abstract translation: 公开了一种制造半导体器件的方法。 该方法包括以下步骤：将沟槽定义为具有有源区域和场区域的半导体衬底的场区域; 用可流动的绝缘层部分地填充沟槽; 通过在沟槽中的可流动绝缘层上沉积紧密堆积的绝缘层，通过隔离结构完全填充沟槽; 蚀刻通过所述紧密封装绝缘层的一部分并蚀刻成所述绝缘结构的可流动绝缘层的部分厚度以暴露所述有源区的一部分; 清洁具有相对投影的活性区域的所得基材; 在清洁步骤中发生弯曲的可流动绝缘层的蚀刻部分上形成间隔物; 以及在所述有源区和所述绝缘结构上形成栅极以与所述有源区的所述暴露部分相接触。

公开(公告)号：US20070148840A1

公开(公告)日：2007-06-28

申请号：US11594579

申请日：2006-11-08

Applicant: Dong Sun Sheen ,  Seok Pyo Song ,  Sang Tae Ahn ,  Hyun Chul Sohn

Inventor： Dong Sun Sheen ,  Seok Pyo Song ,  Sang Tae Ahn ,  Hyun Chul Sohn

IPC: H01L21/8234

CPC classification number: H01L21/823437 ,  H01L29/66795 ,  H01L29/7851

Abstract: A fin transistor is formed by forming a hard mask layer on a substrate having an active region and a field region. The hard mask layer is etched to expose the field region. A trench is formed by etching the exposed field region. The trench is filled with an SOG layer. The hard mask layer is removed to expose the active region. An epi-silicon layer is formed on the exposed active region. The SOG layer is then partially etched from the upper end of the trench, thus filling a lower portion of the trench. A HDP oxide layer is deposited on the etched SOG layer filling the trench, thereby forming a field oxide layer composed of the SOG layer and the HDP oxide. The HDP oxide layer in the field oxide layer is etched to expose both side surfaces of the epi-silicon layer. A gate is then formed on the epi-silicon layer of which both side surfaces are exposed and the field oxide layer.

Abstract translation: 通过在具有有源区域和场区域的衬底上形成硬掩模层来形成鳍式晶体管。 蚀刻硬掩模层以暴露场区域。 通过蚀刻暴露的场区形成沟槽。 沟槽填充有SOG层。 去除硬掩模层以暴露活性区域。 在暴露的有源区上形成外延硅层。 然后从沟槽的上端部分地蚀刻SOG层，从而填充沟槽的下部。 HDP氧化物层沉积在填充沟槽的蚀刻SOG层上，从而形成由SOG层和HDP氧化物构成的场氧化物层。 蚀刻场氧化物层中的HDP氧化物层以露出外延硅层的两个侧表面。 然后在其两个侧表面暴露的外延硅层和场氧化物层上形成栅极。

公开(公告)号：US07687371B2

公开(公告)日：2010-03-30

申请号：US12243133

申请日：2008-10-01

Applicant: Dong Sun Sheen ,  Seok Pyo Song ,  Sang Tae Ahn ,  Hyeon Ju An

Inventor： Dong Sun Sheen ,  Seok Pyo Song ,  Sang Tae Ahn ,  Hyeon Ju An

IPC: H01L21/76

CPC classification number: H01L21/76224

Abstract: An isolation structure of a semiconductor device is formed by forming a hard mask layer on a semiconductor substrate having active and field regions to expose the field region. A trench is defined by etching the exposed field region of the semiconductor substrate using the hard mask as an etch mask. An SOG layer is formed in the trench partially filling the trench. An amorphous aluminum oxide layer is formed on the resultant substrate including the SOG layer. An HDP layer is formed on the amorphous aluminum oxide layer to completely fill the trench. The HDP layer and the amorphous aluminum oxide layer are subjected to CMP to expose the hard mask. The hard mask and portions of the amorphous aluminum oxide layer that are formed on the HDP layer are removed. The amorphous aluminum oxide layer is crystallized.

Abstract translation: 半导体器件的隔离结构通过在具有活性和场区域的半导体衬底上形成硬掩模层以暴露场区而形成。 通过使用硬掩模作为蚀刻掩模蚀刻半导体衬底的曝光场区来限定沟槽。 SOG层形成在部分填充沟槽的沟槽中。 在包含SOG层的所得基板上形成无定形氧化铝层。 在无定形氧化铝层上形成HDP层以完全填充沟槽。 对HDP层和无定形氧化铝层进行CMP以暴露硬掩模。 去除形成在HDP层上的硬掩模和无定形氧化铝层的部分。 无定形氧化铝层结晶。

公开(公告)号：US07687355B2

公开(公告)日：2010-03-30

申请号：US11965835

申请日：2007-12-28

Applicant: Dong Sun Sheen ,  Seok Pyo Song ,  Young Ho Lee

Inventor： Dong Sun Sheen ,  Seok Pyo Song ,  Young Ho Lee

IPC: H01L21/336

CPC classification number: H01L29/66795 ,  H01L29/7851

Abstract: A method for manufacturing a fin transistor includes forming a trench by etching a semiconductor substrate. A flowable insulation layer is filled in the trench to form a field insulation layer defining an active region. The portion of the flowable insulation layer coming into contact with a gate forming region is etched so as to protrude the gate forming region in the active region. A protective layer over the semiconductor substrate is formed to fill the portion of the etched flowable insulation layer. The portion of the protective layer formed over the active region is removed to expose the active region of the semiconductor substrate. The exposed active region of the semiconductor substrate is cleaned. The protective layer remaining on the portion of the etched flowable insulation layer is removed. Gates are formed over the protruded gate forming regions in the active region.

Abstract translation: 一种制造鳍式晶体管的方法包括：通过蚀刻半导体衬底形成沟槽。 可流动的绝缘层填充在沟槽中以形成限定有源区的场绝缘层。 与栅极形成区域接触的可流动绝缘层的部分被蚀刻以便在有源区域中突出栅极形成区域。 形成半导体衬底上方的保护层以填充该可蚀刻的可流动绝缘层的部分。 在有源区上形成的保护层的部分被去除以暴露半导体衬底的有源区。 清洁半导体衬底的暴露的有源区。 残留在可蚀刻的可流动绝缘层的部分上的保护层被去除。 在活性区域中的突出的栅极形成区域上形成栅极。