公开(公告)号：US08294155B2

公开(公告)日：2012-10-23

申请号：US13187584

申请日：2011-07-21

Applicant: Shunpei Yamazaki ,  Yoshiyuki Kurokawa ,  Yasuhiro Jinbo ,  Satoshi Kobayashi ,  Daisuke Kawae

Inventor： Shunpei Yamazaki ,  Yoshiyuki Kurokawa ,  Yasuhiro Jinbo ,  Satoshi Kobayashi ,  Daisuke Kawae

IPC: H01L29/10

CPC classification number: H01L29/4908 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/04 ,  H01L29/41733 ,  H01L29/66765 ,  H01L29/78696

Abstract: A thin film transistor with excellent electric characteristics, a display device having the thin film transistor, and a method for manufacturing the thin film transistor and the display device are proposed. The thin film transistor includes a gate insulating film formed over a gate electrode, a microcrystalline semiconductor film formed over the gate insulating film, a buffer layer formed over the microcrystalline semiconductor film, a pair of semiconductor films to which an impurity element imparting one conductivity type is added and which are formed over the buffer layer, and wirings formed over the pair of semiconductor films to which the impurity element imparting one conductivity type is added. A part of the gate insulating film or the entire gate insulating film, and/or a part of the microcrystalline semiconductor or the entire microcrystalline semiconductor includes an impurity element which serves as a donor.

Abstract translation: 提出了具有优异电特性的薄膜晶体管，具有薄膜晶体管的显示装置，以及制造薄膜晶体管和显示装置的方法。 薄膜晶体管包括形成在栅电极上的栅极绝缘膜，形成在栅极绝缘膜上的微晶半导体膜，形成在微晶半导体膜上的缓冲层，一对半导体膜，赋予一种导电型的杂质元素 并且形成在缓冲层之上，并且在添加有赋予一种导电类型的杂质元素的一对半导体膜上形成的布线。 栅极绝缘膜或整个栅极绝缘膜的一部分和/或微晶半导体的一部分或整个微晶半导体包括用作供体的杂质元素。

公开(公告)号：US08289052B2

公开(公告)日：2012-10-16

申请号：US12894881

申请日：2010-09-30

Applicant: Daisuke Kawae

Inventor： Daisuke Kawae

IPC: H03K19/00 ,  H03K19/20 ,  H03K19/094 ,  H01L25/00

CPC classification number: H03K19/09407 ,  G02F1/1362 ,  G02F1/167 ,  G02F2001/1674

Abstract: It is an object to provide a logic circuit which can be operated even when unipolar transistors are used. A logic circuit includes a source follower circuit and a logic circuit an input portion of which is connected to an output portion of the source follower circuit and all transistors are unipolar transistors. A potential of a wiring for supplying a low potential connected to the source follower circuit is lower than a potential of a wiring for supplying a low potential connected to the logic circuit which includes unipolar transistors. In this manner, a logic circuit which can be operated even with unipolar depletion transistors can be provided.

Abstract translation: 本发明的目的是提供即使在使用单极晶体管时也可以进行操作的逻辑电路。 逻辑电路包括源极跟随器电路和逻辑电路，其输入部分连接到源极跟随器电路的输出部分，所有晶体管都是单极晶体管。 用于提供连接到源极跟随器电路的低电位的布线的电位低于用于提供连接到包括单极晶体管的逻辑电路的低电位的布线的电位。 以这种方式，可以提供甚至可以用单极耗尽晶体管操作的逻辑电路。

公开(公告)号：US08095104B2

公开(公告)日：2012-01-10

申请号：US11812761

申请日：2007-06-21

Applicant: Daisuke Kawae ,  Masami Endo ,  Yoshiyuki Kurokawa ,  Takayuki Ikeda

Inventor： Daisuke Kawae ,  Masami Endo ,  Yoshiyuki Kurokawa ,  Takayuki Ikeda

IPC: H04B1/28

CPC classification number: H03K3/0315 ,  G06F1/04 ,  G06K19/07749 ,  H03K2005/00045 ,  H03K2005/00084

Abstract: A semiconductor device includes an antenna circuit for receiving a wireless signal, a power supply circuit generating power by the wireless signal received by the antenna circuit, and a clock generation circuit to which power is supplied. The clock generation circuit includes a ring oscillator which self-oscillates and a frequency divider which adjusts frequency of an output signal of the ring oscillator in an appropriate range. A digital circuit portion is driven by a clock having high frequency accuracy, so that a malfunction such as an incorrect operation or no response is prevented.

Abstract translation: 半导体器件包括用于接收无线信号的天线电路，通过由天线电路接收的无线信号产生电力的电源电路以及供给电力的时钟产生电路。 时钟发生电路包括自振荡的环形振荡器和将环形振荡器的输出信号的频率调整到适当范围的分频器。 数字电路部分由具有高频精度的时钟驱动，从而防止诸如错误操作或不响应的故障。

公开(公告)号：US20110248268A1

公开(公告)日：2011-10-13

申请号：US13167762

申请日：2011-06-24

Applicant: Koji DAIRIKI ,  Takayuki IKEDA ,  Hidekazu MIYAIRI ,  Yoshiyuki KUROKAWA ,  Hiromichi GODO ,  Daisuke KAWAE ,  Takayuki INOUE ,  Satoshi KOBAYASHI

Inventor： Koji DAIRIKI ,  Takayuki IKEDA ,  Hidekazu MIYAIRI ,  Yoshiyuki KUROKAWA ,  Hiromichi GODO ,  Daisuke KAWAE ,  Takayuki INOUE ,  Satoshi KOBAYASHI

IPC: H01L29/786

CPC classification number: H01L29/78618 ,  H01L29/04 ,  H01L29/41733 ,  H01L29/4908 ,  H01L29/66765 ,  H01L29/78696

Abstract: To improve problems with on-state current and off-state current of thin film transistors, a thin film transistor includes a pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added, provided with a space therebetween; a conductive layer which is overlapped, over the gate insulating layer, with the gate electrode and one of the pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added; and an amorphous semiconductor layer which is provided successively between the pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added in such a manner that the amorphous semiconductor layer extends over the gate insulating layer from the conductive layer and is in contact with both of the pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added.

Abstract translation: 为了改善薄膜晶体管的导通电流和截止电流的问题，薄膜晶体管包括一对杂质半导体层，赋予一种导电类型的杂质元素，在其间具有间隔; 在所述栅极绝缘层上与所述栅电极和添加了赋予一种导电类型的杂质元素的所述一对杂质半导体层中的一个重叠的导电层; 以及非晶半导体层，其被连续地设置在赋予一种导电类型的杂质元素的一对杂质半导体层之间，使得非晶半导体层从导电层延伸到栅极绝缘层上并且接触 同时添加赋予一种导电类型的杂质元素的一对杂质半导体层。

公开(公告)号：US07989332B2

公开(公告)日：2011-08-02

申请号：US12839669

申请日：2010-07-20

Applicant: Shunpei Yamazaki ,  Yoshiyuki Kurokawa ,  Yasuhiro Jinbo ,  Satoshi Kobayashi ,  Daisuke Kawae

Inventor： Shunpei Yamazaki ,  Yoshiyuki Kurokawa ,  Yasuhiro Jinbo ,  Satoshi Kobayashi ,  Daisuke Kawae

IPC: H01L21/3205

CPC classification number: H01L29/4908 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/04 ,  H01L29/41733 ,  H01L29/66765 ,  H01L29/78696

Abstract: A thin film transistor with excellent electric characteristics, a display device having the thin film transistor, and a method for manufacturing the thin film transistor and the display device are proposed. The thin film transistor includes a gate insulating film formed over a gate electrode, a microcrystalline semiconductor film formed over the gate insulating film, a buffer layer formed over the microcrystalline semiconductor film, a pair of semiconductor films to which an impurity element imparting one conductivity type is added and which are formed over the buffer layer, and wirings formed over the pair of semiconductor films to which the impurity element imparting one conductivity type is added. A part of the gate insulating film or the entire gate insulating film, and/or a part of the microcrystalline semiconductor or the entire microcrystalline semiconductor includes an impurity element which serves as a donor.

Abstract translation: 提出了具有优异电特性的薄膜晶体管，具有薄膜晶体管的显示装置，以及制造薄膜晶体管和显示装置的方法。 薄膜晶体管包括形成在栅电极上的栅极绝缘膜，形成在栅极绝缘膜上的微晶半导体膜，形成在微晶半导体膜上的缓冲层，一对半导体膜，赋予一种导电型的杂质元素 并且形成在缓冲层之上，并且在添加有赋予一种导电类型的杂质元素的一对半导体膜上形成的布线。 栅极绝缘膜或整个栅极绝缘膜的一部分和/或微晶半导体的一部分或整个微晶半导体包括用作供体的杂质元素。

公开(公告)号：US20110175091A1

公开(公告)日：2011-07-21

申请号：US13075436

申请日：2011-03-30

Applicant: Satoshi KOBAYASHI ,  Yoshiyuki KUROKAWA ,  Shunpei YAMAZAKI ,  Daisuke KAWAE

Inventor： Satoshi KOBAYASHI ,  Yoshiyuki KUROKAWA ,  Shunpei YAMAZAKI ,  Daisuke KAWAE

IPC: H01L29/786 ,  H01L21/336 ,  H01L33/02

CPC classification number: H01L29/41733 ,  H01L29/04 ,  H01L29/66765 ,  H01L29/78696

Abstract: To provide a display device having a thin film transistor with high electric characteristics and excellent reliability and a manufacturing method thereof. A gate electrode, a gate insulating film provided over the gate electrode, a first semiconductor layer provided over the gate insulating film and having a microcrystalline semiconductor, a second semiconductor layer provided over the first semiconductor layer and having an amorphous semiconductor, and a source region and a drain region provided over the second semiconductor layer are provided. The first semiconductor layer has high crystallinity than the second semiconductor layer. The second semiconductor layer includes an impurity region having a conductivity type different from a conductivity type of the source region and the drain region between the source region and the drain region.

Abstract translation: 提供具有高电特性和优异可靠性的薄膜晶体管的显示装置及其制造方法。 栅电极，设置在栅电极上的栅极绝缘膜，设置在栅绝缘膜上并具有微晶半导体的第一半导体层，设置在第一半导体层上并具有非晶半导体的第二半导体层，以及源极区 并且设置在第二半导体层上的漏极区。 第一半导体层具有比第二半导体层高的结晶度。 第二半导体层包括具有不同于源极区域的导电类型和源极区域与漏极区域之间的漏极区域的导电类型的杂质区域。

公开(公告)号：US07968880B2

公开(公告)日：2011-06-28

申请号：US12391398

申请日：2009-02-24

Applicant: Koji Dairiki ,  Takayuki Ikeda ,  Hidekazu Miyairi ,  Yoshiyuki Kurokawa ,  Hiromichi Godo ,  Daisuke Kawae ,  Takayuki Inoue ,  Satoshi Kobayashi

Inventor： Koji Dairiki ,  Takayuki Ikeda ,  Hidekazu Miyairi ,  Yoshiyuki Kurokawa ,  Hiromichi Godo ,  Daisuke Kawae ,  Takayuki Inoue ,  Satoshi Kobayashi

IPC: H01L29/04 ,  H01L31/036 ,  H01L31/0376 ,  H01L31/20

CPC classification number: H01L29/78618 ,  H01L29/04 ,  H01L29/41733 ,  H01L29/4908 ,  H01L29/66765 ,  H01L29/78696

Abstract: To improve problems with on-state current and off-state current of thin film transistors, a thin film transistor includes a pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added, provided with a space therebetween; a conductive layer which is overlapped, over the gate insulating layer, with the gate electrode and one of the pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added; and an amorphous semiconductor layer which is provided successively between the pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added in such a manner that the amorphous semiconductor layer extends over the gate insulating layer from the conductive layer and is in contact with both of the pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added.

Abstract translation: 为了改善薄膜晶体管的导通电流和截止电流的问题，薄膜晶体管包括一对杂质半导体层，赋予一种导电类型的杂质元素，在其间具有间隔; 在所述栅极绝缘层上与所述栅电极和添加了赋予一种导电类型的杂质元素的所述一对杂质半导体层中的一个重叠的导电层; 以及非晶半导体层，其被连续地设置在赋予一种导电类型的杂质元素的一对杂质半导体层之间，使得非晶半导体层从导电层延伸到栅极绝缘层上并且接触 同时添加赋予一种导电类型的杂质元素的一对杂质半导体层。

公开(公告)号：US20100279474A1

公开(公告)日：2010-11-04

申请号：US12768205

申请日：2010-04-27

Applicant: Kengo AKIMOTO ,  Daisuke KAWAE

Inventor： Kengo AKIMOTO ,  Daisuke KAWAE

IPC: H01L21/336

CPC classification number: H01L27/1225 ,  H01L27/1214 ,  H01L29/7869

Abstract: A formation of a gate electrode provided over an oxide semiconductor layer of a thin film transistor is performed together with a patterning of the oxide semiconductor layer.

Abstract translation: 在薄膜晶体管的氧化物半导体层上设置的栅电极的形成与氧化物半导体层的图案化一起进行。

公开(公告)号：US20100032679A1

公开(公告)日：2010-02-11

申请号：US12504897

申请日：2009-07-17

Applicant: Daisuke KAWAE ,  Yoshiyuki KUROKAWA ,  Hidekazu MIYAIRI

Inventor： Daisuke KAWAE ,  Yoshiyuki KUROKAWA ,  Hidekazu MIYAIRI

IPC: H01L33/00

CPC classification number: H01L29/78696 ,  H01L27/1214 ,  H01L27/1288 ,  H01L29/04 ,  H01L29/66765 ,  H01L29/78645

Abstract: A thin film transistor whose threshold voltage can be controlled and which has a favorable switching characteristic is provided. The thin film transistor includes a first gate electrode layer; a semiconductor layer; a first gate insulating layer provided between the first gate electrode layer and the semiconductor layer; source electrode and drain electrode layers which are provided over the semiconductor layer; a conductive layer covered by the first gate insulating layer and the semiconductor layer and provided so as to overlap with part of the first gate electrode layer; a second gate insulating layer provided so as to cover at least a back channel portion of the semiconductor layer; and a second gate electrode layer provided over the second gate insulating layer so as to overlap with the back channel portion of the semiconductor layer.

Abstract translation: 提供了可以控制阈值电压并具有良好的开关特性的薄膜晶体管。 薄膜晶体管包括第一栅电极层; 半导体层; 设置在所述第一栅极电极层和所述半导体层之间的第一栅极绝缘层; 源电极和漏极电极层，设置在半导体层上; 由第一栅极绝缘层和半导体层覆盖的导电层，并且设置成与第一栅极电极层的一部分重叠; 第二栅极绝缘层，设置成覆盖半导体层的至少后沟道部分; 以及第二栅极电极层，设置在所述第二栅极绝缘层上方以与所述半导体层的所述后部沟道部重叠。

公开(公告)号：US20080211561A1

公开(公告)日：2008-09-04

申请号：US12021843

申请日：2008-01-29

Applicant: Yoshiyuki Kurokawa ,  Takayuki Ikeda ,  Masami Endo ,  Hiroki Dembo ,  Daisuke Kawae ,  Takayuki Inoue ,  Munehiro Kozuma

Inventor： Yoshiyuki Kurokawa ,  Takayuki Ikeda ,  Masami Endo ,  Hiroki Dembo ,  Daisuke Kawae ,  Takayuki Inoue ,  Munehiro Kozuma

IPC: H03K3/00

CPC classification number: G06F7/68 ,  G06F1/025 ,  G06F1/04 ,  H04L7/033

Abstract: The semiconductor device is provided with a clock signal generation circuit that includes a reference clock signal generation circuit which generates a first reference clock signal, a first counter circuit which counts the number of rising edges of the first reference clock signal by using the first reference clock signal and a synchronizing signal, a second counter circuit which counts the number of rising edges of the first reference clock signal by using an enumerated value of the first counter circuit, a first divider circuit which divides a frequency of the first reference clock signal by using the enumerated value of the first counter circuit and generates a second reference clock signal, and a second divider circuit which divides a frequency of the second reference clock signal and generates a clock signal.

Abstract translation: 半导体器件设置有时钟信号产生电路，其包括产生第一参考时钟信号的参考时钟信号产生电路，第一计数器电路，通过使用第一参考时钟对第一参考时钟信号的上升沿进行计数 信号和同步信号;第二计数器电路，通过使用第一计数器电路的枚举值对第一参考时钟信号的上升沿数进行计数;第一除法器电路，其使用第一参考时钟信号的频率进行分频; 第一计数器电路的枚举值并产生第二参考时钟信号，以及第二除法器电路，其分频第二参考时钟信号的频率并产生时钟信号。