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    MULTIPHASE LOW LC BUCK REGULATOR
    1.
    发明申请
    MULTIPHASE LOW LC BUCK REGULATOR 有权
    多相低LC降压调节器

    公开(公告)号：US20140021931A1

    公开(公告)日：2014-01-23

    申请号：US14009740

    申请日：2011-06-06

    申请人： Deepak Pancholi ,  Bhavin Odedara

    发明人： Deepak Pancholi ,  Bhavin Odedara

    IPC分类号： H02M1/08

    CPC分类号： H02M1/08 ,  H02M3/1584

    摘要： A buck power converter creates a desired output voltage from a greater input voltage with higher efficiency than linear regulators or charge pumps. For compact-size and cost sensitive products, the use of the buck power converter is hindered mainly because of lack of physical space and increases in the cost of the passive components like the inductor and capacitor. Techniques are presented to reduce the sizes of the passive components so that they can be integrated on-chip or in-package or on board. A signal converter in the buck power converter determines the duty cycle of a switching control signal. The switching control signal would ordinarily have driven a power switching circuit that provides current to the inductor in the buck power converter. The signal converter outputs a modified (multiphase) switching control signal that includes multiple separated on-periods that taken together approximate the duty cycle of the switching control signal while maintaining the same control loop frequency. The multiphase switching signal drives the power switching circuit to provide current to the inductor during each of the multiple separated on-periods so that the output voltage ripple decreases by a factor of the number of phases in the modified switching signal. In this way, if the ripple amplitude is kept same, the sizes of the passive components can be reduced by the factor of the number of phases in the modified switching control signal.

    摘要翻译： 降压功率转换器从更大的输入电压产生所需的输出电压，效率高于线性稳压器或电荷泵。 对于紧凑型和成本敏感的产品，降低功率转换器的使用主要是由于物理空间不足以及无源器件（如电感器和电容器）的成本增加而受到阻碍。 提出了减少无源元件尺寸的技术，使其可以集成在片上或封装内或板上。 降压功率转换器中的信号转换器确定开关控制信号的占空比。 开关控制信号通常会驱动向降压功率转换器中的电感器提供电流的功率开关电路。 信号转换器输出修改的（多相）开关控制信号，其包括多个分离的接通周期，其大致接近开关控制信号的占空比，同时保持相同的控制回路频率。 多相开关信号驱动功率开关电路，以在多个分离的导通周期中的每一个期间向电感器提供电流，使得输出电压纹波在修改的开关信号中的相位数量减小。 以这种方式，如果纹波幅度保持相同，则可以通过修改的开关控制信号中的相数的因数来减小无源部件的尺寸。

    Self-calibrating relaxation oscillator based clock source
    2.
    发明授权
    Self-calibrating relaxation oscillator based clock source 有权
    基于自校准弛豫振荡器的时钟源

    公开(公告)号：US08085099B2

    公开(公告)日：2011-12-27

    申请号：US12754836

    申请日：2010-04-06

    申请人： Deepak Pancholi ,  Bhavin Odedara ,  Naidu Prasad ,  Srikanth Bojja ,  Srinivasa Rao Sabbineni ,  Jayaprakash Naradasi

    发明人： Deepak Pancholi ,  Bhavin Odedara ,  Naidu Prasad ,  Srikanth Bojja ,  Srinivasa Rao Sabbineni ,  Jayaprakash Naradasi

    IPC分类号： H03L7/085 ,  H03K3/02

    CPC分类号： H03L7/099 ,  H03K3/0231 ,  H03K4/502 ,  H03L7/089

    摘要： A technique and corresponding circuitry are presented for a process independent, self-calibrating relaxation based clock source. The technique and circuitry presented here can reduce the time and cost needed for calibration significantly. The relaxation based clock source produces a clock signal whose frequency is dependent upon a trim value. Starting from an initial trim value, the clock signal is generated, its frequency is compared with a reference clock frequency value, and the trim value is correspondingly adjusted up or down a bit at a time. After this process has continued for a while, min-max logic is used to determine the maximum and minimum trim values and, based on these, the final trim value for the clock is set. This calibration process can also be used to extract whether, and by how much, the implementation on silicon of a particular chip lies in the fast or slow process corners.

    摘要翻译： 提出了一种技术和相应的电路，用于独立于过程的自校准弛豫时钟源。 这里介绍的技术和电路可以显着减少校准所需的时间和成本。 基于弛豫的时钟源产生时钟信号，其频率取决于修整值。 从初始微调值开始，产生时钟信号，将其频率与参考时钟频率值进行比较，并且每次相应地调整微调值上下调整。 在该过程持续一段时间后，使用最小 - 最大逻辑来确定最大和最小修剪值，并且基于这些值，设置时钟的最终修整值。 该校准过程也可用于提取特定芯片的硅上的实现是否以及多少，处于快速或慢速的工艺角落。

    Self-calibrating relaxation oscillator based clock cycle
    4.
    发明授权
    Self-calibrating relaxation oscillator based clock cycle 有权
    基于时钟周期的自校准弛豫振荡器

    公开(公告)号：US08669817B2

    公开(公告)日：2014-03-11

    申请号：US13300808

    申请日：2011-11-21

    申请人： Deepak Pancholi ,  Bhavin Odedara ,  Naidu Prasad ,  Srikanth Bojja ,  Srinivasa Rao Sabbineni ,  Jayaprakash Naradasi

    发明人： Deepak Pancholi ,  Bhavin Odedara ,  Naidu Prasad ,  Srikanth Bojja ,  Srinivasa Rao Sabbineni ,  Jayaprakash Naradasi

    IPC分类号： H03L7/085 ,  H03K3/02

    CPC分类号： H03L7/099 ,  H03K3/0231 ,  H03K4/502 ,  H03L7/089

    摘要： A technique and corresponding circuitry are presented for a process independent, self-calibrating relaxation based clock source. The technique and circuitry presented here can reduce the time and cost needed for calibration significantly. The relaxation based clock source produces a clock signal whose frequency is dependent upon a trim value. Starting from an initial trim value, the clock signal is generated, its frequency is compared with a reference clock frequency value, and the trim value is correspondingly adjusted up or down a bit at a time. After this process has continued for a while, min-max logic is used to determine the maximum and minimum trim values and, based on these, the final trim value for the clock is set. This calibration process can also be used to extract whether, and by how much, the implementation on silicon of a particular chip lies in the fast or slow process corners.

    摘要翻译： 提出了一种技术和相应的电路，用于独立于过程的自校准弛豫时钟源。 这里介绍的技术和电路可以显着减少校准所需的时间和成本。 基于弛豫的时钟源产生时钟信号，其频率取决于修整值。 从初始微调值开始，产生时钟信号，将其频率与参考时钟频率值进行比较，并且每次相应地调整微调值上下调整。 在该过程持续一段时间后，使用最小 - 最大逻辑来确定最大和最小修剪值，并且基于这些值，设置时钟的最终修整值。 该校准过程也可用于提取特定芯片的硅上的实现是否以及多少，处于快速或慢速的工艺角落。

    Controlled load regulation and improved response time of LDO with adaptive current distribution mechanism
    6.
    发明授权
    Controlled load regulation and improved response time of LDO with adaptive current distribution mechanism 有权
    采用自适应电流分配机制控制负载调节和改善LDO响应时间

    公开(公告)号：US08471538B2

    公开(公告)日：2013-06-25

    申请号：US12693228

    申请日：2010-01-25

    申请人： Deepak Pancholi ,  Bhavin Odedara ,  Naidu Prasad

    发明人： Deepak Pancholi ,  Bhavin Odedara ,  Naidu Prasad

    IPC分类号： G05F1/00

    CPC分类号： G05F1/575

    摘要： A low drop-out (LDO) voltage regulation circuit includes first and second internal current paths. The first internal current path is between the input supply voltage and ground and includes the regulator's buffer circuit. The second internal current path is between the input supply voltage and ground and includes the regulator's power transistor. The amount of current flowing through the first internal current path relative to the amount of current flowing through the second internal current path is an increasing function of a current supplied to a load connected to the output supply node. The load regulation of the LDO is improved as the DC gain will not go down at lower load currents. Further, the no load to full load response time is improved as the load pole and power MOS gate pole are actively controlled with respect to output load current. In this mechanism, as the amount of current being supplied to the load decreases, the internal current flow shifts from the first internal current path to the second internal current path and vice versa. This arrangement maintains the desired pole structure and keeps the quiescent current largely the same for all load current levels.

    摘要翻译： 低压差（LDO）电压调节电路包括第一和第二内部电流路径。 第一条内部电流路径位于输入电源电压和地之间，并包括稳压器的缓冲电路。 第二个内部电流路径位于输入电源电压和地之间，并包括稳压器的功率晶体管。 流过第一内部电流路径的电流相对于流过第二内部电流路径的电流量是提供给连接到输出电源节点的负载的电流的增加函数。 由于直流增益在较低的负载电流下不会下降，所以LDO的负载调节得到改善。 此外，随着负载极和功率MOS栅极相对于输出负载电流被主动地控制，空载负载响应时间得到改善。 在该机构中，当供给到负载的电流量减少时，内部电流从第一内部电流路径移动到第二内部电流路径，反之亦然。 这种布置保持所需的极结构并且在所有负载电流水平下保持静态电流大体相同。

    Partial Feedback Mechanism in Voltage Regulators to Reduce Output Noise Coupling and DC Voltage Shift at Output
    7.
    发明申请
    Partial Feedback Mechanism in Voltage Regulators to Reduce Output Noise Coupling and DC Voltage Shift at Output 审中-公开
    电压调节器的部分反馈机制，用于降低输出噪声耦合和输出时的直流电压偏移

    公开(公告)号：US20110133710A1

    公开(公告)日：2011-06-09

    申请号：US12632998

    申请日：2009-12-08

    申请人： Deepak Pancholi ,  Ekram Bhuiyan ,  Steve Chi ,  Naidu Prasad ,  Bhavin Odedara

    发明人： Deepak Pancholi ,  Ekram Bhuiyan ,  Steve Chi ,  Naidu Prasad ,  Bhavin Odedara

    IPC分类号： G05F1/10

    CPC分类号： G05F1/575

    摘要： Techniques are presented for reducing the DC voltage shift in a voltage regulator, particularly for high and ultra-high speed load switching operation. The regulator includes a power transistor, connected between an input supply voltage and an output node, and an error amplifier, having its output connected to control the gate of the output transistor, a first input connected to receive a reference voltage, and a second input connected to a feedback node. The regulator also includes a first resistance, connected between the feedback node and ground, and also a second resistance, a third resistance, and a first capacitance, where the feedback node is connected to the output node through a combination of the first capacitance in parallel with the second resistance and in series with the third resistance. Consequently, the feedback path from the output node of the regulator uses a partial feedback mechanism, where the capacitance is included to generate a zero in the feedback divider path, but a resistance is placed in series with the capacitance so that at high frequencies the feedback level is still separated from the output level.

    摘要翻译： 提出了降低电压调节器中的直流电压偏移的技术，特别是对于高速和超高速负载切换操作。 调节器包括连接在输入电源电压和输出节点之间的功率晶体管，以及误差放大器，其输出被连接以控制输出晶体管的栅极，连接到接收参考电压的第一输入端和第二输入端 连接到反馈节点。 调节器还包括连接在反馈节点和地之间的第一电阻，以及第二电阻，第三电阻和第一电容，其中反馈节点通过并联的第一电容的组合连接到输出节点 具有第二阻力并与第三阻力串联。 因此，来自调节器的输出节点的反馈路径使用部分反馈机制，其中包括电容以在反馈分配器路径中产生零，但是电阻与电容串联放置，使得在高频时反馈 级别仍然与输出级别分离。

    Supply noise current control circuit in bypass mode
    9.
    发明授权
    Supply noise current control circuit in bypass mode 有权
    在旁路模式下提供噪声电流控制电路

    公开(公告)号：US09098101B2

    公开(公告)日：2015-08-04

    申请号：US13772865

    申请日：2013-02-21

    申请人： Prasad Naidu ,  Deepak Pancholi

    发明人： Prasad Naidu ,  Deepak Pancholi

    IPC分类号： G05F1/00 ,  G05F1/10 ,  G05F3/02

    CPC分类号： G05F1/10 ,  G05F1/56

    摘要： A proposed inrush control circuit may work in the presence of supply noise. A linear regulator in bypass mode may be designed for inrush current control, but may be susceptible to irregularities from increased supply noise. The circuit may include a splitting of the bypass power MOS that are switched on with some delay during the power on to control the initial power-on inrush current.

    摘要翻译： 提出的浪涌控制电路可能在存在供电噪声的情况下工作。 旁路模式中的线性稳压器可以设计用于浪涌电流控制，但可能会受到不断增加的电源噪声的影响。 电路可以包括在通电期间以一定延迟被接通的旁路功率MOS的分离，以控制初始上电浪涌电流。

    METAL-OXIDE-METAL CAPACITOR STRUCTURE
    10.
    发明申请
    METAL-OXIDE-METAL CAPACITOR STRUCTURE 有权
    金属氧化物 - 金属电容器结构

    公开(公告)号：US20140103490A1

    公开(公告)日：2014-04-17

    申请号：US13772916

    申请日：2013-02-21

    申请人： Santhosh Kumar ,  Smitha Naganna ,  Deepak Pancholi

    发明人： Santhosh Kumar ,  Smitha Naganna ,  Deepak Pancholi

    IPC分类号： H01L49/02

    CPC分类号： H01L28/60 ,  H01G4/232 ,  H01L23/5223 ,  H01L28/86 ,  H01L28/90 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A capacitor from a Metal-Oxide-Metal (“MoM”) process may include a plurality of metal layers arranged with different design structures. The metal layers may be connected with vias. The metal layers may include wires, such as rows and/or fingers that are arranged for maximizing capacitance between adjacent fingers, as well as between fingers of different metal layers. As the spacing of the fingers is increased, the reliability, yield of final product, and ease of manufacturing both increase. The capacitor increases the spacing of wires/fingers while either maintaining or improving the capacitance per unit area.

    摘要翻译： 来自金属 - 氧化物 - 金属（“MoM”）工艺的电容器可以包括布置有不同设计结构的多个金属层。 金属层可以与通孔连接。 金属层可以包括诸如行和/或指状物的布线，其布置成使相邻指状物之间的电容最大化，以及不同金属层的指状物之间。 随着手指的间距增加，最终产品的可靠性，产量和制造容易度都增加。 电容器增加电线/手指的间距，同时保持或改善每单位面积的电容。