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    Structure and method for protecting memory cells from UV radiation damage and UV radiation-induced charging during backend processing
    1.
    发明授权
    Structure and method for protecting memory cells from UV radiation damage and UV radiation-induced charging during backend processing 有权
    用于保护记忆细胞免受后期处理中的紫外线辐射损伤和紫外线辐射诱导的充电的结构和方法

    公开(公告)号：US06974989B1

    公开(公告)日：2005-12-13

    申请号：US10841933

    申请日：2004-05-06

    Applicant: Cinti X. Chen ,  Boon-Yong Ang ,  Hajime Wada ,  Sameer S. Haddad ,  Inkuk Kang

    Inventor： Cinti X. Chen ,  Boon-Yong Ang ,  Hajime Wada ,  Sameer S. Haddad ,  Inkuk Kang

    IPC: H01L21/8246 ,  H01L21/8247 ,  H01L27/108 ,  H01L27/115

    CPC classification number: H01L27/115 ,  H01L27/11521 ,  H01L27/11568

    Abstract: According to one exemplary embodiment, a structure comprises a substrate. The structure further comprises at least one memory cell situated on the substrate. The structure further comprises a first interlayer dielectric layer situated over the at least one memory cell and over the substrate. The structure further comprises an oxide cap layer situated on the first interlayer dielectric layer. According to this exemplary embodiment, the structure further comprises an etch stop layer comprising TCS nitride situated on the oxide cap layer, where the etch stop layer blocks UV radiation. The structure further comprises a second interlayer dielectric layer situated on the etch stop layer. The structure may further comprise a trench situated in the second interlayer dielectric layer and the etch stop layer, where the trench is filled with copper. The structure may further comprise an anti-reflective coating layer situated on the second interlayer dielectric layer.

    Abstract translation: 根据一个示例性实施例，一种结构包括基底。 该结构还包括位于基板上的至少一个存储单元。 所述结构还包括位于所述至少一个存储单元上并位于所述衬底之上的第一层间介电层。 该结构还包括位于第一层间介电层上的氧化物覆盖层。 根据该示例性实施例，该结构还包括位于氧化物覆盖层上的包含TCS氮化物的蚀刻停止层，其中蚀刻停止层阻挡UV辐射。 该结构还包括位于蚀刻停止层上的第二层间介电层。 该结构还可以包括位于第二层间电介质层和蚀刻停止层中的沟槽，其中沟槽被铜填充。 该结构还可以包括位于第二层间介电层上的抗反射涂层。

    Identifying non-randomness in integrated circuit product yield
    2.
    发明授权
    Identifying non-randomness in integrated circuit product yield 有权
    识别集成电路产品中的非随机性

    公开(公告)号：US08311659B1

    公开(公告)日：2012-11-13

    申请号：US12556071

    申请日：2009-09-09

    Applicant: Cinti X. Chen ,  Joe W. Zhao

    Inventor： Cinti X. Chen ,  Joe W. Zhao

    IPC: G06F19/00

    CPC classification number: H01L22/20

    Abstract: A method of analyzing integrated circuit (IC) product yield can include storing, within a memory of a system comprising a processor, parametric data from a manufacturing process of an IC and determining a measure of non-random variation for at least one parameter of the parametric data using a pattern detection technique. The processor can compare the measure of non-random variation to a randomness criteria and selectively output a notification indicating that variation in the parameter is non-random according to the comparison of the measure of non-random variation to the randomness criteria.

    Abstract translation: 分析集成电路（IC）产品产量的方法可以包括在包括处理器的系统的存储器内存储来自IC的制造过程的参数数据，并且确定至少一个参数的非随机变量的度量 使用模式检测技术的参数数据。 处理器可以将非随机变化的度量与随机性标准进行比较，并且根据非随机变量的度量与随机性标准的比较，选择性地输出指示参数的变化是非随机的通知。

    Structure and method for preventing UV radiation damage and increasing data retention in memory cells
    4.
    发明授权
    Structure and method for preventing UV radiation damage and increasing data retention in memory cells 有权
    用于防止紫外线辐射损伤并增加记忆单元中数据保留的结构和方法

    公开(公告)号：US06765254B1

    公开(公告)日：2004-07-20

    申请号：US10460279

    申请日：2003-06-12

    Applicant: Angela Hui ,  Minh V. Ngo ,  Ning Cheng ,  Jaeyong Park ,  Jean Y. Yang ,  Hidehiko Shiraiwa ,  Rinji Sugino ,  Tazrien Kamal ,  Cinti X. Chen

    Inventor： Angela Hui ,  Minh V. Ngo ,  Ning Cheng ,  Jaeyong Park ,  Jean Y. Yang ,  Hidehiko Shiraiwa ,  Rinji Sugino ,  Tazrien Kamal ,  Cinti X. Chen

    IPC: H01L27108

    CPC classification number: H01L27/115 ,  H01L23/552 ,  H01L27/11521 ,  H01L27/11568 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: According to one exemplary embodiment, a structure comprises a substrate. The structure further comprises at least one memory cell situated on the substrate. The at least one memory cell may be, for example, a flash memory cell, such as a SONOS flash memory cell. The structure further comprises an interlayer dielectric layer situated over the at least one memory cell and over the substrate. According to this exemplary embodiment, the structure further comprises a UV radiation blocking layer which comprises silicon-rich TCS nitride. Further, an oxide cap layer is situated over the UV radiation blocking layer. The structure might further comprise an antireflective coating layer over the oxide cap layer. The interlayer dielectric may comprise BPSG and the oxide cap layer may comprise TEOS oxide.

    Abstract translation: 根据一个示例性实施例，一种结构包括基底。 该结构还包括位于基板上的至少一个存储单元。 至少一个存储单元可以是例如闪存单元，例如SONOS闪存单元。 所述结构还包括位于所述至少一个存储器单元上方并位于所述衬底之上的层间电介质层。 根据该示例性实施例，该结构还包括包含富含硅的TCS氮化物的UV辐射阻挡层。 此外，氧化物覆盖层位于UV辐射阻挡层上。 该结构还可以包括氧化物覆盖层上的抗反射涂层。 层间电介质可以包括BPSG，并且氧化物覆盖层可以包含TEOS氧化物。

    Increasing circuit speed and reducing circuit leakage by utilizing a local surface temperature effect
    5.
    发明授权
    Increasing circuit speed and reducing circuit leakage by utilizing a local surface temperature effect 有权
    通过利用局部表面温度效应提高电路速度并减少电路漏电

    公开(公告)号：US08402412B1

    公开(公告)日：2013-03-19

    申请号：US13112896

    申请日：2011-05-20

    Applicant: Cinti X. Chen ,  Xiao-Yu Li ,  Joe W. Zhao

    Inventor： Cinti X. Chen ,  Xiao-Yu Li ,  Joe W. Zhao

    IPC: G06F17/50

    CPC classification number: H01L27/0251 ,  G06F17/5072 ,  H01L27/0207 ,  H01L27/11807 ,  H01L29/0692

    Abstract: An embodiment of an integrated circuit is disclosed. For this embodiment, the integrated circuit includes circuit blocks. At least one transistor of a circuit block of the circuit blocks includes a portion of a semiconductor substrate having a diffusion layer. The circuit block has a relatively high diffusion pattern density as compared with others of the circuit blocks. The diffusion layer has an exposed surface active area constrained responsive to a design rule. The design rule is to limit to a maximum amount the surface active area in order to improve at least one parameter of the at least one transistor selected from a group consisting of an increase in switching speed and a decrease in leakage current of the at least one transistor of the circuit block having the relatively high diffusion pattern density.

    Abstract translation: 公开了一种集成电路的实施例。 对于该实施例，集成电路包括电路块。 电路块的电路块的至少一个晶体管包括具有扩散层的半导体衬底的一部分。 与其他电路块相比，电路块具有相对较高的扩散图案密度。 扩散层具有受到响应于设计规则约束的暴露表面有源面积的限制。 设计规则是限制到表面有效面积的最大量，以便改进至少一个晶体管的至少一个参数，该至少一个晶体管选自由开关速度的增加和至少一个的开关速度的降低引起的 具有较高扩散图案密度的电路块的晶体管。

    Estimating Icc current temperature scaling factor of an integrated circuit
    6.
    发明授权
    Estimating Icc current temperature scaling factor of an integrated circuit 有权
    估计集成电路的Icc当前温度比例因子

    公开(公告)号：US08166445B1

    公开(公告)日：2012-04-24

    申请号：US12558109

    申请日：2009-09-11

    Applicant: Cinti X. Chen ,  Yongjun Zheng ,  Joe W. Zhao

    Inventor： Cinti X. Chen ,  Yongjun Zheng ,  Joe W. Zhao

    IPC: G06F17/50

    CPC classification number: G06F17/5036

    Abstract: An embodiment of the present invention reduces resources needed to estimate the Icc Current Temperature Scaling Factor (ITSF) of a device, and provides a method and apparatus to estimate ITSF from the device speed and performance characteristics which can be measured at room temperature. In one embodiment, a method for estimating the ITSF of an integrated circuit includes: determining a level of propagation delay of a portion of the integrated circuit; and determining an estimated Icc current temperature scaling factor from a correlation between the level of the propagation delay and a modeled Icc current temperature scaling factor.

    Abstract translation: 本发明的实施例减少了估计装置的Icc电流温度比例因子（ITSF）所需的资源，并且提供了一种从室温下测量的装置速度和性能特征估计ITSF的方法和装置。 在一个实施例中，用于估计集成电路的ITSF的方法包括：确定集成电路的一部分的传播延迟的水平; 以及根据传播延迟的电平和建模的Icc当前温度比例因子之间的相关性来确定估计的Icc当前温度比例因子。

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