公开(公告)号：US07336518B2

公开(公告)日：2008-02-26

申请号：US11383727

申请日：2006-05-16

Applicant: Soo-Bong Chang ,  Chi-Wook Kim

Inventor： Soo-Bong Chang ,  Chi-Wook Kim

IPC: G11C5/02

CPC classification number: G11C7/1048 ,  G11C7/062 ,  G11C11/4091 ,  G11C11/4093

Abstract: A memory device includes a memory cell array block including memory cells, a word line driver block adjacent the memory cell array block disposed in a direction in which word lines of the memory cells are arranged, a sense amplifier block adjacent the memory cell array block disposed in a direction in which bit lines of the memory cells are arranged, a conjunction block disposed at an intersection of the word line driver block and the sense amplifier block, an equalizer for equalizing a pair of local data lines, the equalizer disposed in the conjunction block, and a local data line sense amplifier configured to sense and amplify signals on a pair of local data lines, and having transistors of a first type disposed in the conjunction block and transistors of a second type disposed in the sense amplifier block.

Abstract translation: 存储器件包括存储单元阵列块，存储单元阵列块，与沿着存储单元的字线排列的方向布置的存储单元阵列块相邻的字线驱动块，设置有存储单元阵列块的读出放大器块 在布置存储单元的位线的方向上，设置在字线驱动块和读出放大器块的交叉点处的连接块，用于均衡一对本地数据线的均衡器，均衡器配置在一起 块和本地数据线读出放大器，其被配置为感测和放大一对本地数据线上的信号，并且具有布置在连接块中的第一类型的晶体管和布置在读出放大器块中的第二类型的晶体管。

公开(公告)号：US07161823B2

公开(公告)日：2007-01-09

申请号：US11134855

申请日：2005-05-19

Applicant: Jae-Young Lee ,  Joon-Hyuk Kwon ,  Chi-Wook Kim ,  Sung-Hoon Kim ,  Youn-Sik Park

Inventor： Jae-Young Lee ,  Joon-Hyuk Kwon ,  Chi-Wook Kim ,  Sung-Hoon Kim ,  Youn-Sik Park

IPC: G11C5/06

CPC classification number: G11C5/14 ,  G11C5/063 ,  G11C11/4074

Abstract: Method and apparatus for use, e.g., with Synchronous Dynamic Random Access Memory (SDRAM) circuits are disclosed. In one described embodiment, three metal layers are deposited and patterned in turn overlying a memory array portion of an SDRAM. Relatively wide power conductors are routed on a third metal layer, allowing power conductors to be reduced in size, or in some cases eliminated, on first and second metal layers. The relatively wide power conductors thus can provide a more stable power supply to the memory array, and also free some space on first and/or second metal for routing of additional and/or more widely spaced signal conductors. Other embodiments are described and claimed.

Abstract translation: 公开了使用例如同步动态随机存取存储器（SDRAM）电路的方法和装置。 在一个所描述的实施例中，沉积三层金属层并依次叠置在SDRAM的存储器阵列部分上。 相对宽的电力导体在第三金属层上布线，允许在第一和第二金属层上的电力导体的尺寸减小或在某些情况下被消除。 因此，相对宽的电力导体可以向存储器阵列提供更稳定的电源，并且还释放第一和/或第二金属上的一些空间，用于路由额外的和/或更广泛间隔的信号导体。 描述和要求保护其他实施例。

公开(公告)号：US20050281114A1

公开(公告)日：2005-12-22

申请号：US10951053

申请日：2004-09-27

Applicant: Hyung-Chan Choi ,  Chi-Wook Kim ,  Byung-Hoon Jeong

Inventor： Hyung-Chan Choi ,  Chi-Wook Kim ,  Byung-Hoon Jeong

IPC: G11C7/02 ,  G11C5/00 ,  G11C5/14 ,  G11C11/407

CPC classification number: G11C5/147 ,  G11C5/14

Abstract: Decoupling capacitance of at least one shared capacitor is distributed among a plurality of voltage sources for enhanced performance with minimized area of a semiconductor device. The high nodes and the low nodes of such voltage sources each comprise at least two distinct nodes for lower noise at the voltage sources. The present invention is applied to particular advantage for coupling a variable number of shared capacitors to a data charge voltage source depending on a bit organization of the semiconductor device.

Abstract translation: 至少一个共享电容器的去耦电容分布在多个电压源之间，以便在半导体器件的面积最小的情况下提高性能。 这些电压源的高节点和低节点各自包括至少两个不同的节点，用于在电压源处降低噪声。 本发明应用于根据半导体器件的位组织将可变数量的共用电容器耦合到数据充电电压源的特别优点。

公开(公告)号：US06898139B2

公开(公告)日：2005-05-24

申请号：US10773024

申请日：2004-02-05

Applicant: Jae-woong Lee ,  Chi-wook Kim ,  Sang-seok Kang

Inventor： Jae-woong Lee ,  Chi-wook Kim ,  Sang-seok Kang

IPC: G11C11/40 ,  G11C7/10 ,  G11C7/22 ,  G11C29/14 ,  G11C7/00

CPC classification number: G11C29/12015 ,  G11C7/1051 ,  G11C7/22 ,  G11C29/14

Abstract: Integrated circuit memory devices include a memory cell array that is configured to output data bits in parallel at a first data rate. An output circuit is configured to serially output the data bits to an external terminal at the first data rate in a normal mode of operation, and to serially output the data bits to the external terminal at a second data rate that is lower than the first data rate in a test mode of operation. Accordingly, the memory cell array can operate at a first data rate while allowing the output circuit to output data to an external terminal at a second data rate that is lower than the first data rate, in a test mode of operation.

Abstract translation: 集成电路存储器件包括被配置为以第一数据速率并行输出数据位的存储单元阵列。 输出电路被配置为在正常操作模式下以第一数据速率将数据位串行地输出到外部终端，并且以低于第一数据的第二数据速率将数据位串行输出到外部终端 在测试操作模式下的速率。 因此，在测试操作模式下，存储单元阵列可以以第一数据速率工作，同时允许输出电路以低于第一数据速率的第二数据速率将数据输出到外部终端。

公开(公告)号：US06526473B1

公开(公告)日：2003-02-25

申请号：US09440728

申请日：1999-11-16

Applicant: Chi-wook Kim

Inventor： Chi-wook Kim

IPC: G06F1202

CPC classification number: G11C7/1006 ,  G11C5/04

Abstract: A memory module system for connecting only selected memory modules to a data line to control data input and output is disclosed. The memory module system has a multiplicity of memory modules for outputting data to a data bus line, and more particularly, only the memory modules outputting data is electrically connected to the data bus line in response to activation of a predetermined connection control signal. The connection control signal has an activation width corresponding to a burst length of the output data. Only selected memory modules are connected to the data line during the data burst length, so that load per data pin is minimized, to thereby improve speed of writing and reading data.

Abstract translation: 公开了一种用于将所选存储器模块连接到数据线以控制数据输入和输出的存储器模块系统。 存储器模块系统具有用于将数据输出到数据总线的多个存储器模块，更具体地，响应于预定连接控制信号的激活，仅有输出数据的存储器模块电连接到数据总线。 连接控制信号具有对应于输出数据的突发长度的激活宽度。 在数据突发长度期间，只有选定的存储器模块连接到数据线，从而使每个数据引脚的负载最小化，从而提高写入和读取数据的速度。

公开(公告)号：US07298199B2

公开(公告)日：2007-11-20

申请号：US11291194

申请日：2005-12-01

Applicant: Han-Gyun Jung ,  Chi-Wook Kim

Inventor： Han-Gyun Jung ,  Chi-Wook Kim

IPC: G05F1/10

CPC classification number: G05F3/205

Abstract: A substrate voltage generating circuit for use in a semiconductor memory device is provided. The semiconductor memory device includes a charge pump for generating a substrate bias voltage in response to a clock signal; a first inverter type detector for detecting whether the substrate bias voltage reaches a target voltage; a second differential amplifier type detector for detecting whether the substrate bias voltage reaches the target voltage; and a driver for generating the clock signal in response to an output of one of the first and second detectors.

Abstract translation: 提供了一种用于半导体存储器件的衬底电压产生电路。 半导体存储器件包括用于响应于时钟信号产生衬底偏置电压的电荷泵; 第一反相器型检测器，用于检测衬底偏置电压是否达到目标电压; 第二差分放大器类型检测器，用于检测衬底偏置电压是否达到目标电压; 以及用于响应于第一和第二检测器之一的输出而产生时钟信号的驱动器。

公开(公告)号：US07110316B2

公开(公告)日：2006-09-19

申请号：US10951053

申请日：2004-09-27

Applicant: Hyung-Chan Choi ,  Chi-Wook Kim ,  Byung-Hoon Jeong

Inventor： Hyung-Chan Choi ,  Chi-Wook Kim ,  Byung-Hoon Jeong

IPC: G11C5/14

CPC classification number: G11C5/147 ,  G11C5/14

Abstract: Decoupling capacitance of at least one shared capacitor is distributed among a plurality of voltage sources for enhanced performance with minimized area of a semiconductor device. The high nodes and the low nodes of such voltage sources each comprise at least two distinct nodes for lower noise at the voltage sources. The present invention is applied to particular advantage for coupling a variable number of shared capacitors to a data charge voltage source depending on a bit organization of the semiconductor device.

Abstract translation: 至少一个共享电容器的去耦电容分布在多个电压源之间，以便在半导体器件的面积最小的情况下提高性能。 这些电压源的高节点和低节点各自包括至少两个不同的节点，用于在电压源处降低噪声。 本发明应用于根据半导体器件的位组织将可变数量的共享电容器耦合到数据充电电压源的特别优点。

公开(公告)号：US07068083B2

公开(公告)日：2006-06-27

申请号：US10738876

申请日：2003-12-17

Applicant: Min-Soo Kim ,  Chi-Wook Kim

Inventor： Min-Soo Kim ,  Chi-Wook Kim

IPC: H03K3/00

CPC classification number: G11C29/022 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C11/401 ,  G11C11/4076 ,  G11C11/4093 ,  G11C29/02 ,  G11C29/50 ,  G11C29/50012

Abstract: An output buffer includes an output terminal, a pull up module, a pull down module and an output latching module. The pull up module pulls up the output terminal to a first source voltage when the pull up module is active The pull down module pulls down the output terminal to a second source voltage when the pull down module is active. The output latching module latches a data signal in response to a state of an output clock signal in a first operation mode. The output latching module latches the data signal in response to a leading edge of the output clock signal in a second operation mode. The output latching module drives the pull up module and the pull down module in response to the data signal latched by the output latching module, so that the output latching module outputs the data signal to the output terminal in a second operation mode.

Abstract translation: 输出缓冲器包括输出端子，上拉模块，下拉模块和输出锁存模块。 当上拉模块处于活动状态时，上拉模块将输出端子上拉至第一个源电压当下拉模块处于活动状态时，下拉模块将输出端子下拉至第二个源极电压。 输出锁存模块在第一操作模式下响应于输出时钟信号的状态来锁存数据信号。 输出锁存模块在第二操作模式下响应于输出时钟信号的前沿而锁存数据信号。 输出锁存模块响应于由输出锁存模块锁存的数据信号驱动上拉模块和下拉模块，使得输出锁存模块在第二操作模式下将数据信号输出到输出端子。

公开(公告)号：US06324119B1

公开(公告)日：2001-11-27

申请号：US09557619

申请日：2000-04-25

Applicant: Chi-wook Kim

Inventor： Chi-wook Kim

IPC: G11C700

CPC classification number: G11C7/1084 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/109 ,  G11C7/1093 ,  G11C11/4093

Abstract: A data input circuit of a semiconductor memory device is disclosed. The data input circuit includes a control signal generation circuit, an internal strobe generation circuit and a data setup circuit. The control signal generation circuit generates a strobe control signal activated during input of data of the predetermined burst length. The internal strobe generation circuit generates an internal data strobe signal. The internal data strobe signal synchronizes with an external data strobe signal, and is disabled when data of the predetermined burst length is input. The data setup circuit converts sequentially input data to parallel data in response to the internal data strobe signal. According to the data input circuit and the data input method of the present invention, data of “high”-impedance cannot be input to the semiconductor memory device.

Abstract translation: 公开了一种半导体存储器件的数据输入电路。 数据输入电路包括控制信号发生电路，内部选通脉冲发生电路和数据建立电路。 控制信号产生电路产生在预定突发长度的数据输入期间激活的选通控制信号。 内部选通脉冲发生电路产生内部数据选通信号。 内部数据选通信号与外部数据选通信号同步，并且在输入预定突发长度的数据时被禁止。 数据设置电路响应于内部数据选通信号将顺序输入的数据转换成并行数据。 根据本发明的数据输入电路和数据输入方法，“高”阻抗的数据不能输入到半导体存储器件。

公开(公告)号：US6087851A

公开(公告)日：2000-07-11

申请号：US70894

申请日：1998-04-30

Applicant: Chi-wook Kim ,  Kyung-woo Kang

Inventor： Chi-wook Kim ,  Kyung-woo Kang

IPC: G11C11/413 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  H03K19/0175

CPC classification number: H03K19/017581

Abstract: A semiconductor device can be configured for compatibility with different system level interfaces, e.g., LVTTL or SSTL, after assembly, thereby eliminating the need for bonding options and reducing the cost of manufacturing the device. The device includes an interface dependent circuit that operates with a selected interface in response to one or more interface enable signals. Several alternative embodiments include interface control circuits and mode register circuits for generating the interface enable signals responsive to a row address and control signals such as RAS, CAS, WE, and CS. Some embodiments also include a switching network that allows an input buffer to use an internally generated reference voltage for one interface and an externally applied reference voltage for a second interface.

Abstract translation: 半导体器件可以被配置为在组装之后与不同系统级接口（例如LVTTL或SSTL）兼容，从而消除对接合选项的需要并降低制造器件的成本。 该装置包括一个接口相关电路，该电路响应于一个或多个接口使能信号而与所选择的接口一起操作。 几个替代实施例包括接口控制电路和模式寄存器电路，用于响应于行地址和诸如RAS，CAS，WE和CS的控制信号来产生接口使能信号。 一些实施例还包括允许输入缓冲器对于一个接口使用内部产生的参考电压的开关网络和用于第二接口的外部施加的参考电压。