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1.发明申请公开(公告)号：US20140127496A1
公开(公告)日：2014-05-08
申请号：US14154497
申请日：2014-01-14
申请人： Wen-Huai YU , Cheng-Jui YANG , Yu-Min YANG , Kai-Yuan PAI , Wen-Chieh LAN , Chan-Lu SU , Yu-Tsung CHIANG , Sung-Lin HSU , Wen-Ching HSU , Chung-Wen LAN
发明人： Wen-Huai YU , Cheng-Jui YANG , Yu-Min YANG , Kai-Yuan PAI , Wen-Chieh LAN , Chan-Lu SU , Yu-Tsung CHIANG , Sung-Lin HSU , Wen-Ching HSU , Chung-Wen LAN
CPC分类号： C01B33/02 , C30B11/002 , C30B11/006 , C30B29/06 , H01L31/182 , Y02E10/546 , Y02P70/521 , Y10T428/259
摘要： A crystalline silicon ingot and a method of fabricating the same are provided. The method utilizes a nucleation promotion layer to facilitate a plurality of silicon grains to nucleate on the nucleation promotion layer from a silicon melt and grow in a vertical direction into silicon grains until the silicon melt is completely solidified. The increment rate of defect density in the silicon ingot along the vertical direction has a range of 0.01%/mm˜10%/mm.
摘要翻译： 提供一种晶体硅锭及其制造方法。 该方法利用成核促进层促进多个硅晶粒在硅熔体上在成核促进层上成核并在垂直方向上生长成硅晶粒，直到硅熔体完全固化。 硅锭沿垂直方向的缺陷密度增加率为0.01％/ mm〜10％/ mm。
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公开(公告)号：US08533639B2
公开(公告)日：2013-09-10
申请号：US13233453
申请日：2011-09-15
申请人： Mei-Hsuan Lin , Chih-Chan Lu , Chih-Hsun Lin , Chih-Kang Chao , Ling-Sung Wang , Jen-Pan Wang
发明人： Mei-Hsuan Lin , Chih-Chan Lu , Chih-Hsun Lin , Chih-Kang Chao , Ling-Sung Wang , Jen-Pan Wang
CPC分类号： G06F17/50 , G06F17/5072 , H01L21/823412 , H01L21/823418 , H01L21/823475 , H01L21/823481 , H01L25/00 , H01L27/0207 , H01L27/11 , H01L27/12 , H01L29/788 , H01L2924/0002 , H03K19/00 , H01L2924/00
摘要： The present disclosure provides an integrated circuit design method. In an example, a method includes receiving an integrated circuit design layout that includes an active region feature, a contact feature, and an isolation feature, wherein a portion of the active region feature is disposed between the contact feature and the isolation feature; determining whether a thickness of the portion of the active region feature disposed between the contact feature and the isolation feature is less than a threshold value; and modifying the integrated circuit design layout if the thickness is less than the threshold value, wherein the modifying includes adding a supplementary active region feature adjacent to the portion of the active region feature disposed between the contact feature and the isolation feature.
摘要翻译： 本公开提供了一种集成电路设计方法。 在一个示例中，一种方法包括接收包括有源区域特征，接触特征和隔离特征的集成电路设计布局，其中有源区域特征的一部分设置在接触特征和隔离特征之间; 确定布置在接触特征和隔离特征之间的有源区域特征的部分的厚度是否小于阈值; 以及如果所述厚度小于所述阈值，则修改所述集成电路设计布局，其中所述修改包括在所述接触特征与所述隔离特征之间的所述有源区域特征的所述部分附近添加辅助有源区域特征。
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4.发明申请RETAINING RING FOR CHEMICAL MECHANICAL POLISHING, ITS OPERATIONAL METHOD AND APPLICATION SYSTEM 审中-公开化学机械抛光保持环及其操作方法和应用系统公开(公告)号：US20090023362A1
公开(公告)日：2009-01-22
申请号：US11778650
申请日：2007-07-17
申请人： Tzu-Shin Chen , Chih-Chin Yang , Min-Hao Yeh , Kai-Chun Yang , Chan Lu , Tzu-Hui Wu , Cheng-Hsun Wu
发明人： Tzu-Shin Chen , Chih-Chin Yang , Min-Hao Yeh , Kai-Chun Yang , Chan Lu , Tzu-Hui Wu , Cheng-Hsun Wu
摘要： A retaining ring for CMP is disclosed. The retaining ring has a plurality of grooves. The grooves have rounded sidewalls. Because the sidewalls of the grooves of the retaining ring are rounded, the slurry is not apt to accumulate around them and the pad is less scratched. Accordingly, the micro-scratches on the wafer surface are reduced and the yield of the CMP step is increased. Its operational method and application system are also disclosed in this invention.
摘要翻译： 公开了一种用于CMP的保持环。 保持环具有多个槽。 凹槽具有圆形的侧壁。 由于保持环的槽的侧壁是圆形的，所以浆料不易于在其周围积聚，并且垫较少划伤。 因此，晶片表面上的微划痕减小，并且CMP步骤的产量增加。 其操作方法和应用系统也在本发明中公开。
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公开(公告)号：US20080261402A1
公开(公告)日：2008-10-23
申请号：US11736006
申请日：2007-04-17
申请人： Chan Lu , Teng-Chun Tsai , Chih-Yueh Li , Kai-Gin Yang , Chien-Chung Huang , Chia-Hsi Chen , Tzu-Hui Wu
发明人： Chan Lu , Teng-Chun Tsai , Chih-Yueh Li , Kai-Gin Yang , Chien-Chung Huang , Chia-Hsi Chen , Tzu-Hui Wu
IPC分类号： H01L21/302
CPC分类号： H01L21/31053 , H01L21/02065
摘要： A method of removing an insulating layer on a substrate is described, including a first CMP process and a second CMP process performed in sequence, wherein the polishing slurry used in the first CMP process and that used in the second CMP process have substantially the same pH value that exceeds 7.0. A cleaning step is conducted between the first and the second CMP processes to remove a specific substance which would otherwise cause undesired particles to form in the second CMP process.
摘要翻译： 描述了去除衬底上的绝缘层的方法，包括依次执行的第一CMP工艺和第二CMP工艺，其中在第一CMP工艺中使用的抛光浆料和在第二CMP工艺中使用的抛光浆料具有基本上相同的pH 价值超过7.0。 在第一和第二CMP工艺之间进行清洁步骤以除去否则会在第二CMP工艺中导致不期望的颗粒形成的特定物质。
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6.发明申请SOLUTION FOR FIXED ABRASIVE CHEMICAL MECHANICAL POLISHING PROCESS AND FIXED ABRASIVE CHEMICAL MECHANICAL POLISHING METHOD 审中-公开固定磨料化学机械抛光工艺和固定磨料化学机械抛光方法的解决方案公开(公告)号：US20080125018A1
公开(公告)日：2008-05-29
申请号：US11563579
申请日：2006-11-27
申请人： CHAN LU , TENG-CHUN TSAI , CHIH-YUEH LI , KAI-GIN YANG
发明人： CHAN LU , TENG-CHUN TSAI , CHIH-YUEH LI , KAI-GIN YANG
CPC分类号： C09K3/1463 , C09G1/02
摘要： A solution for fixed abrasive chemical mechanical polishing process including a protection constituent, a hydrolysis constituent and water is described. The protection constituent is used to protect a silicon nitride and its concentration is between 0.001 wt % and 10 wt %. The hydrolysis constituent is used to hydrolyze a silicon oxide and its concentration is between 0.001 wt % and 10 wt %. The concentration ofthe water is between 80 wt % and 99.998 wt %.
摘要翻译： 描述了包括保护组分，水解组分和水的固定磨料化学机械抛光方法。 保护成分用于保护氮化硅，其浓度在0.001wt％至10wt％之间。 水解成分用于水解氧化硅，其浓度在0.001wt％至10wt％之间。 水的浓度在80wt％至99.998wt％之间。
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7.发明授权Method of fabricating crystalline silicon ingot including nucleation promotion layer 有权包括成核促进层的晶体硅锭的制造方法公开(公告)号：US09493357B2
公开(公告)日：2016-11-15
申请号：US13416525
申请日：2012-03-09
申请人： Wen-Huai Yu , Cheng-Jui Yang , Yu-Min Yang , Kai-Yuan Pai , Wen-Chieh Lan , Chan-Lu Su , Yu-Tsung Chiang , Sung-Lin Hsu , Wen-Ching Hsu , Chung-Wen Lan
发明人： Wen-Huai Yu , Cheng-Jui Yang , Yu-Min Yang , Kai-Yuan Pai , Wen-Chieh Lan , Chan-Lu Su , Yu-Tsung Chiang , Sung-Lin Hsu , Wen-Ching Hsu , Chung-Wen Lan
CPC分类号： C01B33/02 , C30B11/002 , C30B11/006 , C30B29/06 , H01L31/182 , Y02E10/546 , Y02P70/521 , Y10T428/259
摘要： A crystalline silicon ingot and a method of fabricating the same are provided. The method utilizes a nucleation promotion layer to facilitate a plurality of silicon grains to nucleate on the nucleation promotion layer from a silicon melt and grow in a vertical direction into silicon grains until the silicon melt is completely solidified. The increment rate of defect density in the silicon ingot along the vertical direction has a range of 0.01%/mm˜10%/mm.
摘要翻译： 提供一种晶体硅锭及其制造方法。 该方法利用成核促进层促进多个硅晶粒在硅熔体上在成核促进层上成核并在垂直方向上生长成硅晶粒，直到硅熔体完全固化。 硅锭沿垂直方向的缺陷密度增加率为0.01％/ mm〜10％/ mm。
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8.发明申请公开(公告)号：US20130136918A1
公开(公告)日：2013-05-30
申请号：US13416525
申请日：2012-03-09
申请人： Wen-Huai YU , Cheng-Jui YANG , Yu-Min YANG , Kai-Yuan PAI , Wen-Chieh LAN , Chan-Lu SU , Yu-Tsung CHIANG , Sung-Lin HSU , Wen-Ching HSU , Chung-Wen LAN
发明人： Wen-Huai YU , Cheng-Jui YANG , Yu-Min YANG , Kai-Yuan PAI , Wen-Chieh LAN , Chan-Lu SU , Yu-Tsung CHIANG , Sung-Lin HSU , Wen-Ching HSU , Chung-Wen LAN
CPC分类号： C01B33/02 , C30B11/002 , C30B11/006 , C30B29/06 , H01L31/182 , Y02E10/546 , Y02P70/521 , Y10T428/259
摘要： A crystalline silicon ingot and a method of fabricating the same are provided. The method utilizes a nucleation promotion layer to facilitate a plurality of silicon grains to nucleate on the nucleation promotion layer from a silicon melt and grow in a vertical direction into silicon grains until the silicon melt is completely solidified. The increment rate of defect density in the silicon ingot along the vertical direction has a range of 0.01%/mm˜10%/mm.
摘要翻译： 提供一种晶体硅锭及其制造方法。 该方法利用成核促进层促进多个硅晶粒在硅熔体上在成核促进层上成核并在垂直方向上生长成硅晶粒，直到硅熔体完全固化。 硅锭沿垂直方向的缺陷密度增量率为0.01％/ mm〜10％/ mm。
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公开(公告)号：US20130069162A1
公开(公告)日：2013-03-21
申请号：US13233453
申请日：2011-09-15
申请人： Mei-Hsuan Lin , Chih-Chan Lu , Chih-Hsun Lin , Chih-Kang Chao , Ling-Sung Wang , Jen-Pan Wang
发明人： Mei-Hsuan Lin , Chih-Chan Lu , Chih-Hsun Lin , Chih-Kang Chao , Ling-Sung Wang , Jen-Pan Wang
IPC分类号： H01L27/088 , G06F17/50
CPC分类号： G06F17/50 , G06F17/5072 , H01L21/823412 , H01L21/823418 , H01L21/823475 , H01L21/823481 , H01L25/00 , H01L27/0207 , H01L27/11 , H01L27/12 , H01L29/788 , H01L2924/0002 , H03K19/00 , H01L2924/00
摘要： The present disclosure provides an integrated circuit design method. In an example, a method includes receiving an integrated circuit design layout that includes an active region feature, a contact feature, and an isolation feature, wherein a portion of the active region feature is disposed between the contact feature and the isolation feature; determining whether a thickness of the portion of the active region feature disposed between the contact feature and the isolation feature is less than a threshold value; and modifying the integrated circuit design layout if the thickness is less than the threshold value, wherein the modifying includes adding a supplementary active region feature adjacent to the portion of the active region feature disposed between the contact feature and the isolation feature.
摘要翻译： 本公开提供了一种集成电路设计方法。 在一个示例中，一种方法包括接收包括有源区域特征，接触特征和隔离特征的集成电路设计布局，其中有源区域特征的一部分设置在接触特征和隔离特征之间; 确定布置在接触特征和隔离特征之间的有源区域特征的部分的厚度是否小于阈值; 以及如果所述厚度小于所述阈值，则修改所述集成电路设计布局，其中所述修改包括在所述接触特征与所述隔离特征之间的所述有源区域特征的所述部分附近添加辅助有源区域特征。
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