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16 条记录 (耗时 0.028 秒)

    Semiconductor device
    1.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US07301791B2

    公开(公告)日：2007-11-27

    申请号：US11325311

    申请日：2006-01-05

    申请人： Bryan Atwood ,  Takao Watanabe

    发明人： Bryan Atwood ,  Takao Watanabe

    IPC分类号： G11C15/00

    CPC分类号： G11C7/1075 ,  G11C11/4076 ,  G11C2207/2245

    摘要： A semiconductor device capable of accessing to the memory with a high speed, and comprising a memory with a large capacity. The semiconductor device comprises a plurality of memory banks (Bank) 1 to 3 where the write cycle time is twice as long as the read cycle and each provided with the separate write and read ports, and two cache data banks CD0 and CD1, in which, for example, in the case that an external write instruction with continuous cycles is issued in cycle #2, the data of Bank 2 stored in CD1, Row 2 cannot be written back since Bank 2 is busy with the cycle #1, the data of Bank 0 stored in CD 0, Row 2 can be written back instead.

    摘要翻译： 一种半导体器件，能够以高速度访问存储器，并且包括具有大容量的存储器。 半导体器件包括多个存储体（存储体）1至3，其中写入周期时间是读取周期的两倍，并且每个具有单独的写入和读取端口以及两个缓存数据组CD 0和CD 1， 例如，在循环＃2中发出具有连续周期的外部写入指令的情况下，存储在CD 1，行2中的存储体2的数据不能被写回，因为存储体2忙于循环＃1 ，存储在CD 0，第2行中的Bank 0的数据可以写回。

    Semiconductor integrated circuit
    2.
    发明授权
    Semiconductor integrated circuit 失效
    半导体集成电路

    公开(公告)号：US07139214B2

    公开(公告)日：2006-11-21

    申请号：US11033157

    申请日：2005-01-12

    申请人： Bryan Atwood ,  Takao Watanabe

    发明人： Bryan Atwood ,  Takao Watanabe

    IPC分类号： G11C8/00

    CPC分类号： G11C11/405

    摘要： An apparatus and method to reduce, during standby time, electric power caused by the leakage current flowing through a storage transistor in a 3-transistor dynamic cell. Source electrodes of storage transistors in a plurality of 3-transistor dynamic cells constituting a memory array are connected, and a switch is provided between the source electrode and a power supply terminal. The leakage current during the standby time is interrupted by bringing the switch into a conducting state during the active time, and by bringing the switch into a nonconducting state during the standby time.

    摘要翻译： 一种在待机时间内减少由流过3晶体管动态单元中的存储晶体管的漏电流引起的电力的装置和方法。 构成存储器阵列的多个3晶体管动态单元中的存储晶体管的源极连接，并且在源电极和电源端子之间设置有开关。 在待机时间内，通过在开启时间内将开关置于导通状态，并在待机时间内将开关置于非导通状态，中断了待机时的漏电流。

    Data processor with internal memory structure for processing stream data
    4.
    发明授权
    Data processor with internal memory structure for processing stream data 失效
    具有用于处理流数据的内部存储器结构的数据处理器

    公开(公告)号：US07765250B2

    公开(公告)日：2010-07-27

    申请号：US11271961

    申请日：2005-11-14

    申请人： Takanobu Tsunoda ,  Bryan Atwood ,  Masashi Takada ,  Hiroshi Tanaka

    发明人： Takanobu Tsunoda ,  Bryan Atwood ,  Masashi Takada ,  Hiroshi Tanaka

    IPC分类号： G06F7/38

    CPC分类号： G06F15/16

    摘要： There is provided at least one processor block including a plurality of load store interfaces (801, 804), a plurality of memory banks (821), an input/output port having at least one of an input port (850) and an output port (860), and a crossbar switch (810), and the crossbar switch connects the load store interface, the memory bank and the input/output port to each other and the load store interface constitutes a data processor in order to control a data transfer to the memory bank. Consequently, there is implemented a data processor having a high transfer throughput and a flexibility and efficiently treating stream data.

    摘要翻译： 提供至少一个处理器块，其包括多个加载存储接口（801,804），多个存储体（821），具有输入端口（850）和输出端口（850）中的至少一个的输入/输出端口 （860）和交叉开关（810），并且交叉开关将负载存储接口，存储体和输入/输出端口彼此连接，并且负载存储接口构成数据处理器，以便控制数据传送 到记忆库。 因此，实现了具有高传输吞吐量和灵活性并且有效地处理流数据的数据处理器。

    Semiconductor device
    5.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US07573753B2

    公开(公告)日：2009-08-11

    申请号：US11875633

    申请日：2007-10-19

    申请人： Bryan Atwood ,  Takao Watanabe

    发明人： Bryan Atwood ,  Takao Watanabe

    IPC分类号： G11C7/10

    CPC分类号： G11C7/1075 ,  G11C11/4076 ,  G11C2207/2245

    摘要： A semiconductor device capable of accessing to the memory with a high speed, and including a memory with a large capacity. The semiconductor device includes a plurality of memory banks (Bank) 1 to 3 where the write cycle time is twice as long as the read cycle and each provided with the separate write and read ports, and two cache data banks CD0 and CD1, in which, for example, in the case that an external write instruction with continuous cycles is issued in cycle #2, the data of Bank 2 stored in CD1, Row 2 cannot be written back since Bank 2 is busy with the cycle #1, the data of Bank 0 stored in CD 0, Row 2 can be written back instead.

    摘要翻译： 能够以高速度访问存储器的半导体器件，并且包括具有大容量的存储器。 半导体器件包括多个存储体（存储体）1至3，其中写入周期时间是读取周期的两倍，并且每个具有单独的写入和读取端口以及两个高速缓存数据组CD0和CD1，其中 例如，在循环＃2中发出具有连续周期的外部写入指令的情况下，存储在CD1，行2中的存储体2的数据不能被写回，因为存储体2忙于循环＃1，数据 存储在CD 0中的Bank 0，可以写回第2行。

    Semiconductor integrated circuit
    6.
    发明授权
    Semiconductor integrated circuit 失效
    半导体集成电路

    公开(公告)号：US07391667B2

    公开(公告)日：2008-06-24

    申请号：US11550735

    申请日：2006-10-18

    申请人： Bryan Atwood ,  Takao Watanabe

    发明人： Bryan Atwood ,  Takao Watanabe

    IPC分类号： G11C5/14

    CPC分类号： G11C11/405

    摘要： An apparatus is to reduce, during the standby time, the electric power caused by the leakage current flowing through a storage transistor in a 3-transistor dynamic cell. Source electrodes of storage transistors in a plurality of 3-transistor dynamic cells constituting a memory array are connected, and a switch is provided between the source electrode and a power supply terminal. The leakage current during the standby time is interrupted by bringing the switch into a conducting state during the active time, and by bringing the switch into a nonconducting state during the standby time.

    摘要翻译： 一种装置是在待机时间内减少由流过3晶体管动态单元中的存储晶体管的漏电流引起的电力。 构成存储器阵列的多个3晶体管动态单元中的存储晶体管的源极连接，并且在源电极和电源端子之间设置有开关。 在待机时间内，通过在开启时间内将开关置于导通状态，并在待机时间内将开关置于非导通状态，中断了待机时的漏电流。

    Semiconductor device
    7.
    发明申请
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US20060171236A1

    公开(公告)日：2006-08-03

    申请号：US11325311

    申请日：2006-01-05

    申请人： Bryan Atwood ,  Takao Watanabe

    发明人： Bryan Atwood ,  Takao Watanabe

    IPC分类号： G11C8/00

    CPC分类号： G11C7/1075 ,  G11C11/4076 ,  G11C2207/2245

    摘要： A semiconductor device capable of accessing to the memory with a high speed, and comprising a memory with a large capacity. The semiconductor device comprises a plurality of memory banks (Bank) 1 to 3 where the write cycle time is twice as long as the read cycle and each provided with the separate write and read ports, and two cache data banks CD0 and CD1, in which, for example, in the case that an external write instruction with continuous cycles is issued in cycle #2, the data of Bank 2 stored in CD1, Row 2 cannot be written back since Bank 2 is busy with the cycle #1, the data of Bank 0 stored in CD 0, Row 2 can be written back instead.

    摘要翻译： 一种半导体器件，能够以高速度访问存储器，并且包括具有大容量的存储器。 半导体器件包括多个存储体（存储体）1至3，其中写入周期时间是读取周期的两倍，并且每个具有单独的写入和读取端口以及两个缓存数据组CD 0和CD 1， 例如，在循环＃2中发出具有连续周期的外部写入指令的情况下，存储在CD 1，行2中的存储体2的数据不能被写回，因为存储体2忙于循环＃1 ，存储在CD 0，第2行中的Bank 0的数据可以写回。