公开(公告)号：US09040378B2

公开(公告)日：2015-05-26

申请号：US14309018

申请日：2014-06-19

Applicant: Bo-Young Lee ,  Jong-Wan Choi ,  Dae-Hun Choi ,  Myoung-Bum Lee

Inventor： Bo-Young Lee ,  Jong-Wan Choi ,  Dae-Hun Choi ,  Myoung-Bum Lee

IPC: H01L21/336 ,  H01L27/115 ,  H01L21/28 ,  H01L21/02

CPC classification number: H01L27/11556 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66666 ,  H01L29/7827

Abstract: Methods of forming semiconductor devices including vertical channels and semiconductor devices formed using such methods are provided. The methods may include forming a stack including a plurality of insulating patterns alternating with a plurality of conductive patterns on an upper surface of a substrate and forming a hole through the stack. The hole may expose sidewalls of the plurality of insulating patterns and the plurality of conductive patterns. The sidewalls of the plurality of insulating patterns may be aligned along a first plane that is slanted with respect to the upper surface of the substrate, and midpoints of the respective sidewalls of the plurality of conductive patterns may be aligned along a second plane that is substantially perpendicular to the upper surface of the substrate.

Abstract translation: 提供了使用这种方法形成的包括垂直沟道和半导体器件的半导体器件的形成方法。 所述方法可以包括形成堆叠，其包括与衬底的上表面上的多个导电图案交替的多个绝缘图案，并且通过堆叠形成孔。 孔可以暴露多个绝缘图案和多个导电图案的侧壁。 多个绝缘图案的侧壁可以沿着相对于衬底的上表面倾斜的第一平面对齐，并且多个导电图案的相应侧壁的中点可以沿着基本上 垂直于衬底的上表面。

公开(公告)号：USD718317S1

公开(公告)日：2014-11-25

申请号：US29422918

申请日：2012-05-25

Applicant: Chang-Mo Yang ,  Kyung-Dae Park ,  Bo-Young Lee ,  Hye-Bin Park

Designer： Chang-Mo Yang ,  Kyung-Dae Park ,  Bo-Young Lee ,  Hye-Bin Park

公开(公告)号：USD707253S1

公开(公告)日：2014-06-17

申请号：US29421487

申请日：2012-07-31

Applicant: Chang-Mo Yang ,  Kyung-Dae Park ,  Hye-Bin Park ,  Bo-Young Lee

Designer： Chang-Mo Yang ,  Kyung-Dae Park ,  Hye-Bin Park ,  Bo-Young Lee

公开(公告)号：US08536652B2

公开(公告)日：2013-09-17

申请号：US13224427

申请日：2011-09-02

Applicant: Bo-young Lee ,  Jong-wan Choi ,  Jin-gi Hong ,  Myoung-bum Lee

Inventor： Bo-young Lee ,  Jong-wan Choi ,  Jin-gi Hong ,  Myoung-bum Lee

IPC: H01L29/78

CPC classification number: H01L21/764 ,  H01L27/11521 ,  H01L27/11568

Abstract: A method of manufacturing a non-volatile memory device, can be provided by forming a gate insulating layer and a gate conductive layer on a substrate that includes active regions that are defined by device isolation regions that include a carbon-containing silicon oxide layer. The gate conductive layer and the gate insulating layer can be sequentially etched to expose the carbon-containing silicon oxide layer. The carbon-containing silicon oxide layer can be wet-etched to recess a surface of the carbon-containing silicon oxide layer to below a surface of the substrate. Then, an interlayer insulating layer can be formed between the gate insulating layer and the gate conductive layer on the carbon-containing silicon oxide layer, where an air gap can be formed between the carbon-containing silicon oxide layer and the gate insulating layer.

Abstract translation: 可以通过在包括由包含含碳氧化硅层的器件隔离区限定的有源区的衬底上形成栅极绝缘层和栅极导电层来提供制造非易失性存储器件的方法。 可以依次蚀刻栅极导电层和栅极绝缘层，以露出含碳氧化硅层。 可以对含碳氧化硅层进行湿蚀刻，以将含碳氧化硅层的表面凹入到衬底的表面下方。 然后，可以在含碳氧化硅层上的栅极绝缘层和栅极导电层之间形成层间绝缘层，其中可以在含碳氧化硅层和栅极绝缘层之间形成气隙。

公开(公告)号：US08270556B2

公开(公告)日：2012-09-18

申请号：US12325877

申请日：2008-12-01

Applicant: Bo Young Lee ,  Jae Seong Kim ,  Woong Ki Hwang

Inventor： Bo Young Lee ,  Jae Seong Kim ,  Woong Ki Hwang

IPC: G21C9/00

CPC classification number: G01N17/00 ,  G21C17/00

Abstract: An apparatus for forming stress corrosion cracks comprises a heating unit which includes a conductive member and a heating coil disposed adjacent to the conductive member to generate steam pressure in the tube specimen, an end holding unit, and a control unit for controlling the heating unit and the end holding unit. The stress corrosion cracks occurring in the equipment of nuclear power plants or apparatus industries during operation can be directly formed in a tube specimen using steam pressure under conditions similar to those of the actual environment of nuclear power plants, thus increasing accuracy for analysis of properties of stress corrosion cracks which are in actuality generated, thereby improving reliability of nuclear power plants or apparatus industries and effectively assuring nondestructive testing capability, resulting in very useful industrial applicability.

Abstract translation: 用于形成应力腐蚀裂纹的装置包括加热单元，其包括导电构件和邻近导电构件设置的加热线圈，以在管样本中产生蒸汽压力，端部保持单元和用于控制加热单元的控制单元， 末端保持单元。 核电站或设备工业设备在运行过程中产生的应力腐蚀裂纹，可以直接在管状试样上形成，在与核电厂实际环境条件相似的条件下，采用蒸汽压力，从而提高分析性能的准确性 实际产生的应力腐蚀裂纹，从而提高核电厂或设备行业的可靠性，有效保证无损检测能力，从而产生非常有用的工业应用。

公开(公告)号：US06592753B2

公开(公告)日：2003-07-15

申请号：US10117646

申请日：2002-04-05

Applicant: Bo-Young Lee

Inventor： Bo-Young Lee

IPC: C02F140

CPC classification number: B01D17/0208 ,  B01D17/0211 ,  B01D17/0214 ,  Y10S210/923

Abstract: An oil recovery system, designed to recover oil from oil-contaminated water of a river, lake or sea due to a difference in specific gravity of the liquids. The system includes a 4-stage separation tank 15 having four chambers 51-54. The first chamber 51 includes a hopper-shaped oil floating unit 59 in communication with a piston pump 68 (FIG. 5) and having porous filters 61, 62 therein. The second and third chambers 52, 53 include a plurality of horizontal diaphragms 63 for reducing the processing time for separating oil from water. The system can be continuously operated without being stopped during an oil recovering operation. The oil recovered from discharged pipe 67 is usable so that the system preferably conserves natural resources.

Abstract translation: 一种采油系统，用于由于液体比重差异，从河流，湖泊或海洋的油污水中回收油。 该系统包括具有四个室51-54的四级分离槽15。 第一室51包括与活塞泵68（图5）连通并且其中具有多孔过滤器61,62的料斗形状的油浮动单元59。 第二和第三室52,53包括多个水平隔膜63，用于减少从水中分离油的处理时间。 在油回收操作期间，系统可以连续运行而不停止。 从排出管67回收的油可以使用，使得该系统优选地保存自然资源。

公开(公告)号：US09323427B2

公开(公告)日：2016-04-26

申请号：US13270337

申请日：2011-10-11

Applicant: Seock Hyun Yu ,  Giang Yoon Kwon ,  Chang Mo Yang ,  Jae Myung Lee ,  Yu Sic Kim ,  Bo Young Lee ,  Eun Ju Lee

Inventor： Seock Hyun Yu ,  Giang Yoon Kwon ,  Chang Mo Yang ,  Jae Myung Lee ,  Yu Sic Kim ,  Bo Young Lee ,  Eun Ju Lee

IPC: G06F3/0483 ,  G06F3/0482

CPC classification number: G06F3/0483 ,  G06F3/0482 ,  G06F3/0485 ,  G06F2203/04803

Abstract: A list display method and apparatus are disclosed. The list display method, for a terminal having a display unit, includes detecting a necessity for displaying a list, classifying list items into viewable items and aggregated items, displaying the viewable items in the list view region and displaying information regarding the aggregated items in the list aggregate region. Responsive to inputs aggregate items may be classified as viewable items and corresponding ones of the viewable items are classified as aggregate items.

Abstract translation: 公开了列表显示方法和装置。 列表显示方法，对于具有显示单元的终端，包括检测列表的显示必要性，将列表项分类为可查看项目和聚合项目，将可查看项目显示在列表视图区域中，并且显示有关聚合项目的信息 列表聚合区域。 响应输入的总项可以分类为可查看项目，相应的可查看项目被分类为总项目。

公开(公告)号：US20150060988A1

公开(公告)日：2015-03-05

申请号：US14519821

申请日：2014-10-21

Applicant: Bo-Young LEE ,  Jongwan CHOI ,  Myoungbum LEE

Inventor： Bo-Young LEE ,  Jongwan CHOI ,  Myoungbum LEE

IPC: H01L27/115 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L27/11582 ,  H01L21/76229 ,  H01L21/764 ,  H01L23/528 ,  H01L23/5329 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices, and methods of fabricating the same, include forming a trench between a plurality of patterns on a substrate to be adjacent to each other, forming a first sacrificial layer in the trench, forming a first porous insulation layer having a plurality of pores on the plurality of patterns and on the first sacrificial layer, and removing the first sacrificial layer through the plurality of pores of the first porous insulation layer to form a first air gap between the plurality of patterns and under the first porous insulation layer.

Abstract translation: 半导体器件及其制造方法包括在彼此相邻的衬底上的多个图案之间形成沟槽，在沟槽中形成第一牺牲层，形成具有多个孔的第一多孔绝缘层 所述多个图案和所述第一牺牲层上，并且通过所述第一多孔绝缘层的所述多个孔去除所述第一牺牲层，以在所述多个图案之间和所述第一多孔绝缘层下方形成第一气隙。

公开(公告)号：US08492223B2

公开(公告)日：2013-07-23

申请号：US13085631

申请日：2011-04-13

Applicant: Jong-wan Choi ,  Wan-sik Hwang ,  Gil-heyun Choi ,  Eunkee Hong ,  Ju-seon Goo ,  Bo-young Lee

Inventor： Jong-wan Choi ,  Wan-sik Hwang ,  Gil-heyun Choi ,  Eunkee Hong ,  Ju-seon Goo ,  Bo-young Lee

IPC: H01L21/321

CPC classification number: H01L21/3105 ,  H01L21/76826 ,  H01L27/11521

Abstract: A method of manufacturing a flash memory device includes: forming a dielectric layer on an active region of a substrate having an isolation region and the active region; forming a floating gate on the dielectric layer; forming an isolation layer in the isolation region; forming a nitride layer including a first nitride layer portion formed on an exposed surface of the floating gate and a second nitride layer portion formed on an exposed surface of the isolation layer; selectively removing nitrogen atoms from the second nitride layer portion of the nitride layer; forming an inter-gate dielectric layer on both the first nitride layer portion and the isolation layer; and forming a control gate on the inter-gate dielectric layer.

Abstract translation: 制造闪速存储器件的方法包括：在具有隔离区域和有源区域的衬底的有源区上形成电介质层; 在介电层上形成浮栅; 在隔离区中形成隔离层; 形成包括形成在所述浮置栅极的暴露表面上的第一氮化物层部分和形成在所述隔离层的暴露表面上的第二氮化物层部分的氮化物层; 从氮化物层的第二氮化物层部分选择性地除去氮原子; 在所述第一氮化物层部分和所述隔离层上形成栅极间电介质层; 以及在所述栅极间电介质层上形成控制栅极。

公开(公告)号：US20100230741A1

公开(公告)日：2010-09-16

申请号：US12711033

申请日：2010-02-23

Applicant: Jongwan Choi ,  Eunkee Hong ,  Bo-Young Lee ,  Tae-Jong Han ,  Juseon Goo ,  Kyungmun Byun

Inventor： Jongwan Choi ,  Eunkee Hong ,  Bo-Young Lee ,  Tae-Jong Han ,  Juseon Goo ,  Kyungmun Byun

IPC: H01L29/792 ,  H01L29/06

CPC classification number: H01L29/7881 ,  H01L21/76229 ,  H01L21/764 ,  H01L27/11521 ,  H01L27/11531 ,  H01L27/11568 ,  H01L29/0649

Abstract: A tunnel insulating layer and a charge storage layer are sequentially stacked on a substrate. A recess region penetrates the charge storage layer, the tunnel insulating layer and a portion of the substrate. The recess region is defined by a bottom surface and a side surface extending from the bottom surface. A first dielectric pattern includes a bottom portion covering the bottom surface and inner walls extending from the bottom portion and covering a portion of the side surface of the recess region. A second dielectric pattern is in the recess region between the inner walls of the first dielectric pattern, and the second dielectric pattern enclosing an air gap. The air gap that is enclosed by the second dielectric pattern may extend through a major portion of the second dielectric pattern in a direction away from the bottom surface of the recess region.

Abstract translation: 隧道绝缘层和电荷存储层依次层叠在基板上。 凹陷区域穿透电荷存储层，隧道绝缘层和基底的一部分。 凹陷区域由底表面和从底表面延伸的侧表面限定。 第一电介质图案包括覆盖底面的底部和从底部延伸并覆盖凹部区域的侧表面的一部分的内壁。 第二电介质图案位于第一电介质图案的内壁之间的凹陷区域中，并且第二电介质图案包围气隙。 由第二电介质图案包围的空气间隙可以沿着远离凹部区域的底表面的方向延伸穿过第二电介质图案的主要部分。