公开(公告)号：US20110306195A1

公开(公告)日：2011-12-15

申请号：US13099485

申请日：2011-05-03

Applicant: Jin-Gyun Kim ,  Bo-Young Lee ,  Ki-Hyun Hwang ,  Eunkee Hong ,  Jong-Wan Choi

Inventor： Jin-Gyun Kim ,  Bo-Young Lee ,  Ki-Hyun Hwang ,  Eunkee Hong ,  Jong-Wan Choi

IPC: H01L21/28

CPC classification number: H01L27/11578 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

Abstract: In a vertical semiconductor device and a method of manufacturing a vertical semiconductor device, sacrificial layers and insulating interlayers are repeatedly and alternately stacked on a substrate. The sacrificial layers include boron (B) and nitrogen (N) and have an etching selectivity with respect to the insulating interlayers. Semiconductor patterns are formed on the substrate through the sacrificial layers and the insulating interlayers. The sacrificial layers and the insulating interlayers are at least partially removed between the semiconductor patterns to form sacrificial layer patterns and insulating interlayer patterns on sidewalls of the semiconductor patterns. The sacrificial layer patterns are removed to form grooves between the insulating interlayer patterns. The grooves expose portions of the sidewalls of the semiconductor patterns. A gate structure is formed in each of the grooves.

Abstract translation: 在垂直半导体器件和制造垂直半导体器件的方法中，牺牲层和绝缘夹层重叠交替堆叠在衬底上。 牺牲层包括硼（B）和氮（N），并且相对于绝缘夹层具有蚀刻选择性。 通过牺牲层和绝缘夹层在衬底上形成半导体图案。 在半导体图案之间至少部分去除牺牲层和绝缘夹层，以在半导体图案的侧壁上形成牺牲层图案和绝缘层间图案。 去除牺牲层图案以在绝缘层间图案之间形成凹槽。 凹槽暴露半导体图案的侧壁的部分。 在每个槽中形成栅极结构。

公开(公告)号：US08043914B2

公开(公告)日：2011-10-25

申请号：US12629920

申请日：2009-12-03

Applicant: Jong-wan Choi ,  Yong-soon Choi ,  Bo-young Lee ,  Eunkee Hong ,  Eun-kyung Baek ,  Ju-seon Goo

Inventor： Jong-wan Choi ,  Yong-soon Choi ,  Bo-young Lee ,  Eunkee Hong ,  Eun-kyung Baek ,  Ju-seon Goo

IPC: H01L21/336

CPC classification number: H01L27/11521 ,  H01L27/11524

Abstract: Provided are methods of fabricating flash memory devices that may prevent a short circuit from occurring between cell gate lines. Methods of fabricating such flash memory devices may include forming gate lines including a series of multiple cell gate lines and multiple selection gate lines. Each gate line may include a stacked structure of a tunnel insulating layer, a floating gate, a gate insulating layer, and/or a polysilicon layer operable to be a control gate, all formed on a semiconductor substrate. Methods may include forming a first insulating layer that selectively fills gaps between the cell gate lines from the bottom up and between adjacent ones of the cell gate lines and the selection gate lines, and does not fill a space located on outer sides of the selection gate lines that are opposite the plurality of cell gate lines. A spacer may be formed on the outer sides of the selection gate lines that are opposite to the cell gate lines, after forming the first insulating layer. A second insulating layer may be formed in a space where the spacer is formed.

Abstract translation: 提供了制造闪存器件的方法，其可以防止在单元栅极线之间发生短路。 制造这种闪存器件的方法可以包括形成包括一系列多单元栅极线和多个选择栅极线的栅极线。 每个栅极线可以包括全部形成在半导体衬底上的隧道绝缘层，浮动栅极，栅极绝缘层和/或可操作为控制栅极的多晶硅层的堆叠结构。 方法可以包括形成第一绝缘层，其选择性地从底部向上和相邻的单元栅极线和选择栅极线之间填充单元栅极线之间的间隙，并且不填充位于选择栅极的外侧的空间 与多个单元栅极线相对的线。 在形成第一绝缘层之后，可以在选择栅极线的与单元栅极线相对的外侧上形成间隔物。 可以在形成间隔物的空间中形成第二绝缘层。

公开(公告)号：US20110256708A1

公开(公告)日：2011-10-20

申请号：US13085631

申请日：2011-04-13

Applicant: Jong-wan Choi ,  Wan-sik Hwang ,  Gil-heyun Choi ,  Eunkee Hong ,  Ju-seon Goo ,  Bo-young Lee

Inventor： Jong-wan Choi ,  Wan-sik Hwang ,  Gil-heyun Choi ,  Eunkee Hong ,  Ju-seon Goo ,  Bo-young Lee

IPC: H01L21/321 ,  H01L21/283

CPC classification number: H01L21/3105 ,  H01L21/76826 ,  H01L27/11521

Abstract: A method of manufacturing a flash memory device includes: forming a dielectric layer on an active region of a substrate having an isolation region and the active region; forming a floating gate on the dielectric layer; forming an isolation layer in the isolation region; forming a nitride layer including a first nitride layer portion formed on an exposed surface of the floating gate and a second nitride layer portion formed on an exposed surface of the isolation layer; selectively removing nitrogen atoms from the second nitride layer portion of the nitride layer; forming an inter-gate dielectric layer on both the first nitride layer portion and the isolation layer; and forming a control gate on the inter-gate dielectric layer.

Abstract translation: 制造闪速存储器件的方法包括：在具有隔离区域和有源区域的衬底的有源区上形成电介质层; 在介电层上形成浮栅; 在隔离区中形成隔离层; 形成包括形成在所述浮置栅极的暴露表面上的第一氮化物层部分和形成在所述隔离层的暴露表面上的第二氮化物层部分的氮化物层; 从氮化物层的第二氮化物层部分选择性地除去氮原子; 在所述第一氮化物层部分和所述隔离层上形成栅极间电介质层; 以及在所述栅极间电介质层上形成控制栅极。

公开(公告)号：US20080121977A1

公开(公告)日：2008-05-29

申请号：US11699419

申请日：2007-01-30

Applicant: Yong-Soon Choi ,  Hong-Gun Kim ,  Jong-Wan Choi ,  Eun-Kyung Baek ,  Ju-Seon Goo

Inventor： Yong-Soon Choi ,  Hong-Gun Kim ,  Jong-Wan Choi ,  Eun-Kyung Baek ,  Ju-Seon Goo

IPC: H01L29/788 ,  H01L21/04

CPC classification number: H01L21/76224 ,  H01L27/11521 ,  H01L29/7881

Abstract: A semiconductor device includes a substrate having a trench, a liner layer pattern on sidewalls and a bottom surface of the trench, the liner layer pattern including a first oxide layer pattern and a second oxide layer pattern, a diffusion blocking layer pattern on the liner layer pattern, and an isolation layer pattern in the trench on the diffusion blocking layer pattern.

Abstract translation: 半导体器件包括具有沟槽的衬底，侧壁上的衬垫层图案和沟槽的底表面，衬里层图案包括第一氧化物层图案和第二氧化物层图案，衬垫层上的扩散阻挡层图案 图案和扩散阻挡层图案上的沟槽中的隔离层图案。

公开(公告)号：US20080014711A1

公开(公告)日：2008-01-17

申请号：US11654588

申请日：2007-01-18

Applicant: Jong-Wan Choi ,  Ju-Seon Goo ,  Hong-Gun Kim ,  Yong-Soon Choi ,  Sung-Tae Kim ,  Eun-Kyung Baek

Inventor： Jong-Wan Choi ,  Ju-Seon Goo ,  Hong-Gun Kim ,  Yong-Soon Choi ,  Sung-Tae Kim ,  Eun-Kyung Baek

IPC: H01L21/76

CPC classification number: H01L21/76229 ,  H01L27/105 ,  H01L27/11531

Abstract: Disclosed are methods for fabricating semiconductor devices incorporating a composite trench isolation structure comprising a first oxide pattern, a SOG pattern and a second oxide pattern wherein the oxide patterns enclose the SOG pattern. The methods include the deposition of a first oxide layer and a SOG layer to fill recessed trench regions formed in the substrate. The first oxide layer and the SOG layer are then subjected to a planarization sequence including a CMP process followed by an etchback process to form a composite structure having a substantially flat upper surface that exposes both the oxide and the SOG material. The second oxide layer is then applied and subjected to a similar CMP/etchback sequence to obtain a composite structure having an upper surface that is recessed relative to a plane defined by the surfaces of adjacent active regions.

Abstract translation: 公开了用于制造半导体器件的方法，该半导体器件结合有包括第一氧化物图案，SOG图案和第二氧化物图案的复合沟槽隔离结构，其中氧化物图案包围SOG图案。 所述方法包括沉积第一氧化物层和SOG层以填充形成在衬底中的凹陷沟槽区域。 然后对第一氧化物层和SOG层进行包括CMP工艺的随后的回蚀工艺的平坦化顺序，以形成具有露出氧化物和SOG材料的基本上平坦的上表面的复合结构。 然后施加第二氧化物层并进行类似的CMP /回蚀序列以获得具有相对于由相邻有源区的表面限定的平面凹进的上表面的复合结构。

公开(公告)号：US20120061763A1

公开(公告)日：2012-03-15

申请号：US13224427

申请日：2011-09-02

Applicant: Bo-young LEE ,  Jong-wan Choi ,  Jin-gi Hong ,  Myoung-bum Lee

Inventor： Bo-young LEE ,  Jong-wan Choi ,  Jin-gi Hong ,  Myoung-bum Lee

IPC: H01L29/78 ,  H01L21/283

CPC classification number: H01L21/764 ,  H01L27/11521 ,  H01L27/11568

Abstract: A method of manufacturing a non-volatile memory device, can be provided by forming a gate insulating layer and a gate conductive layer on a substrate that includes active regions that are defined by device isolation regions that include a carbon-containing silicon oxide layer. The gate conductive layer and the gate insulating layer can be sequentially etched to expose the carbon-containing silicon oxide layer. The carbon-containing silicon oxide layer can be wet-etched to recess a surface of the carbon-containing silicon oxide layer to below a surface of the substrate. Then, an interlayer insulating layer can be formed between the gate insulating layer and the gate conductive layer on the carbon-containing silicon oxide layer, where an air gap can be formed between the carbon-containing silicon oxide layer and the gate insulating layer.

Abstract translation: 可以通过在包括由包含含碳氧化硅层的器件隔离区限定的有源区的衬底上形成栅极绝缘层和栅极导电层来提供制造非易失性存储器件的方法。 可以依次蚀刻栅极导电层和栅极绝缘层，以露出含碳氧化硅层。 可以对含碳氧化硅层进行湿蚀刻，以将含碳氧化硅层的表面凹入到衬底的表面下方。 然后，可以在含碳氧化硅层上的栅极绝缘层和栅极导电层之间形成层间绝缘层，其中可以在含碳氧化硅层和栅极绝缘层之间形成气隙。

公开(公告)号：US07674685B2

公开(公告)日：2010-03-09

申请号：US11654588

申请日：2007-01-18

Applicant: Jong-Wan Choi ,  Ju-Seon Goo ,  Hong-Gun Kim ,  Yong-Soon Choi ,  Sung-Tae Kim ,  Eun-Kyung Baek

Inventor： Jong-Wan Choi ,  Ju-Seon Goo ,  Hong-Gun Kim ,  Yong-Soon Choi ,  Sung-Tae Kim ,  Eun-Kyung Baek

IPC: H01L21/76

CPC classification number: H01L21/76229 ,  H01L27/105 ,  H01L27/11531

Abstract: Disclosed are methods for fabricating semiconductor devices incorporating a composite trench isolation structure comprising a first oxide pattern, a SOG pattern and a second oxide pattern wherein the oxide patterns enclose the SOG pattern. The methods include the deposition of a first oxide layer and a SOG layer to fill recessed trench regions formed in the substrate. The first oxide layer and the SOG layer are then subjected to a planarization sequence including a CMP process followed by an etchback process to form a composite structure having a substantially flat upper surface that exposes both the oxide and the SOG material. The second oxide layer is then applied and subjected to a similar CMP/etchback sequence to obtain a composite structure having an upper surface that is recessed relative to a plane defined by the surfaces of adjacent active regions.

Abstract translation: 公开了用于制造半导体器件的方法，该半导体器件结合有包括第一氧化物图案，SOG图案和第二氧化物图案的复合沟槽隔离结构，其中氧化物图案包围SOG图案。 所述方法包括沉积第一氧化物层和SOG层以填充形成在衬底中的凹陷沟槽区域。 然后对第一氧化物层和SOG层进行包括CMP工艺的随后的回蚀工艺的平坦化顺序，以形成具有露出氧化物和SOG材料的基本上平坦的上表面的复合结构。 然后施加第二氧化物层并进行类似的CMP /回蚀序列以获得具有相对于由相邻有源区的表面限定的平面凹进的上表面的复合结构。

公开(公告)号：US07601588B2

公开(公告)日：2009-10-13

申请号：US11267360

申请日：2005-11-04

Applicant: Jong-Wan Choi ,  Hong-Gun Kim ,  Kyu-Tae Na ,  Eunkee Hong

Inventor： Jong-Wan Choi ,  Hong-Gun Kim ,  Kyu-Tae Na ,  Eunkee Hong

IPC: H01L21/336

CPC classification number: H01L27/11521 ,  H01L21/76232 ,  H01L27/115

Abstract: In a method of forming a device isolation layer for minimizing a parasitic capacitor and a non-volatile memory device using the same, a trench is formed on a substrate. A first insulation layer is formed on a top surface of the substrate and on inner surfaces of the trench, so that the trench is partially filled with the first insulation layer. A second insulation layer is formed on the first insulation layer to a thickness to fill up the trench, thereby forming a preliminary isolation layer. An etching rate of the second insulation layer is different from that of the first insulation layer. A recess is formed at a central portion of the preliminary isolation layer by partially removing the first and second insulation layers, thereby forming the device isolation layer including the recess. The recess in the device isolation layer reduces a parasitic capacitance in a non-volatile memory device.

Abstract translation: 在形成用于最小化寄生电容器的器件隔离层和使用其的非易失性存储器件的方法中，在衬底上形成沟槽。 第一绝缘层形成在衬底的顶表面和沟槽的内表面上，使得沟槽部分地被第一绝缘层填充。 在第一绝缘层上形成第二绝缘层至填充沟槽的厚度，从而形成预备隔离层。 第二绝缘层的蚀刻速率与第一绝缘层的蚀刻速率不同。 通过部分去除第一绝缘层和第二绝缘层，在预隔离层的中心部分处形成凹部，从而形成包括凹部的器件隔离层。 器件隔离层中的凹槽降低了非易失性存储器件中的寄生电容。

公开(公告)号：US20090020847A1

公开(公告)日：2009-01-22

申请号：US12216820

申请日：2008-07-11

Applicant: Kyung-Mun Byun ,  Ju-Seon Goo ,  Sang-Ho Rha ,  Eun-Kyung Baek ,  Jong-Wan Choi

Inventor： Kyung-Mun Byun ,  Ju-Seon Goo ,  Sang-Ho Rha ,  Eun-Kyung Baek ,  Jong-Wan Choi

IPC: H01L21/762 ,  H01L23/58

CPC classification number: H01L21/76229

Abstract: A semiconductor device having a trench isolation region and methods of fabricating the same are provided. The method includes forming a first trench region in a substrate, and a second trench region having a larger width than the first trench region in the substrate. A lower material layer may fill the first and second trench regions. The lower material layer may be etched by a first etching process to form a first preliminary lower material layer pattern remaining in the first trench region and form a second preliminary lower material layer pattern that remains in the second trench region. An upper surface of the second preliminary lower material layer pattern may be at a different height than the first preliminary lower material layer pattern. The first and second preliminary lower material layer patterns may be etched by a second etching process to form first and second lower material layer patterns having top surfaces at substantially the same height. First and second upper material layer patterns may be formed on the first and second lower material layer patterns, respectively.

Abstract translation: 提供了具有沟槽隔离区域的半导体器件及其制造方法。 该方法包括在衬底中形成第一沟槽区域和在衬底中具有比第一沟槽区域宽的宽度的第二沟槽区域。 下部材料层可以填充第一和第二沟槽区域。 可以通过第一蚀刻工艺蚀刻下部材料层，以形成残留在第一沟槽区域中的第一初步下部材料层图案，并形成保留在第二沟槽区域中的第二预备下部材料层图案。 第二初步下层材料层图案的上表面可以处于与第一预备下层材料层图案不同的高度。 可以通过第二蚀刻工艺蚀刻第一和第二初级下部材料层图案，以形成具有基本上相同高度的顶表面的第一和第二下部材料层图案。 可以分别在第一和第二下部材料层图案上形成第一和第二上部材料层图案。

公开(公告)号：US20060094203A1

公开(公告)日：2006-05-04

申请号：US11267360

申请日：2005-11-04

Applicant: Jong-Wan Choi ,  Hong-Gun Kim ,  Kyu-Tae Na ,  Eunkee Hong

Inventor： Jong-Wan Choi ,  Hong-Gun Kim ,  Kyu-Tae Na ,  Eunkee Hong

IPC: H01L21/76

CPC classification number: H01L27/11521 ,  H01L21/76232 ,  H01L27/115

Abstract: In a method of forming a device isolation layer for minimizing a parasitic capacitor and a non-volatile memory device using the same, a trench is formed on a substrate. A first insulation layer is formed on a top surface of the substrate and on inner surfaces of the trench, so that the trench is partially filled with the first insulation layer. A second insulation layer is formed on the first insulation layer to a thickness to fill up the trench, thereby forming a preliminary isolation layer. An etching rate of the second insulation layer is different from that of the first insulation layer. A recess is formed at a central portion of the preliminary isolation layer by partially removing the first and second insulation layers, thereby forming the device isolation layer including the recess. The recess in the device isolation layer reduces a parasitic capacitance in a non-volatile memory device.