公开(公告)号：US4740766A

公开(公告)日：1988-04-26

申请号：US92906

申请日：1987-09-04

申请人： Arthur J. Metz

发明人： Arthur J. Metz

IPC分类号： G05F3/22

CPC分类号： G05F3/222

摘要： A precision current generator provides an output current responsive to a reference supply voltage. The current generator comprises a voltage generator which drives the input to a buffer amplifier. The buffer amplifier output drives the bases of multiple output transistors, the collectors of which form the current outputs. The output current is not dependent upon transistor beta, junction voltage, temperature or supply voltage. The all NPN design enables the current generator to track the reference voltage at high frequencies without peaking or ringing of the output current and without voltage coupling between output devices.

公开(公告)号：US4322688A

公开(公告)日：1982-03-30

申请号：US083873

申请日：1979-10-11

申请人： Kenneth G. Schlotzhauer ,  Arthur J. Metz

发明人： Kenneth G. Schlotzhauer ,  Arthur J. Metz

IPC分类号： H03F1/22 ,  H03F1/32 ,  H03F3/45

CPC分类号： H03F3/45103 ,  H03F1/3211

摘要： The cascode feed forward amplifier is modified to correct alpha-induced error. A pair of resistors are serially disposed between the bases of a pair of common-base amplifiers to generate an error voltage proportional to the input signal. The error voltage is applied to the correction amplifier to provide an appropriate correction current.

摘要翻译： 共源共栅前馈放大器被修改以校正α引起的误差。 一对电阻器串联地布置在一对公共基极放大器的基极之间，以产生与输入信号成比例的误差电压。 误差电压被施加到校正放大器以提供适当的校正电流。

公开(公告)号：US5225776A

公开(公告)日：1993-07-06

申请号：US773057

申请日：1991-10-07

申请人： Laszlo J. Dobos ,  Arthur J. Metz

发明人： Laszlo J. Dobos ,  Arthur J. Metz

IPC分类号： G01R1/067 ,  G01R13/34

CPC分类号： G01R13/34 ,  G11C27/02 ,  G11C27/024

摘要： A signal acquisition and sampling system mounted in an oscilloscope probe includes an input buffer amplifier (30) featuring shunt feedback, offset capability, input bias current compensation, and very low input capacitance. Signal sampling is accomplished by a cascaded pair of differential sampling bridges including a fast track-and-hold stage (40) followed by a slow track-and-hold stage (50). The differential configuration of the bridges features common mode rejection of strobe signal coupling into the signal path and reduces aberrations and voltage droop. The fast track-and-hold stage features Schottky diode switching bridges (42A) and (42B), low value storage capacitors (44A) and (44B), thereby resulting in a fast tracking time. The slow track-and-hold stage features low-leakage diode-connected transistor switching bridges (52A) and (52B) and a FET buffer stage, thereby resulting in fast acquisition of the fast stage output and long hold time for quantization of the sample. A strobe signal is coupled through a cable (72) to a timing generator (80) on integrated circuit (20). The strobe signal causes the fast track-and-hold stage to briefly hold samples of the input signal while simultaneously causing the timing generator to drive the slow track-and-hold stage to quickly acquire the output of the fast stage and hold the acquired value for extended time intervals. The bandwidth of the fast stage is thereby combined with the stability of the slow stage.

摘要翻译： 安装在示波器探头中的信号采集和采样系统包括具有分流反馈，偏移能力，输入偏置电流补偿和非常低的输入电容的输入缓冲放大器（30）。 信号采样通过级联的差分采样桥实现，包括快速跟踪和保持阶段（40），随后是缓慢的跟踪和保持阶段（50）。 桥的差分配置具有共模抑制选通信号耦合到信号路径中并减少像差和电压下降。 快速跟踪保持级具有肖特基二极管开关桥（42A）和（42B），低值存储电容（44A）和（44B），从而导致快速的跟踪时间。 慢速跟踪保持级采用低漏二极管连接的晶体管开关桥（52A）和（52B）和FET缓冲级，从而快速获取快速级输出和长时间保持时间，用于量化量程 。 选通信号通过电缆（72）耦合到集成电路（20）上的定时发生器（80）。 选通信号使得快速跟踪和保持级暂时保持输入信号的采样，同时使定时发生器驱动慢速跟踪保持阶段以快速获取快速级的输出并保持所获取的值 延长时间间隔。 因此，快速阶段的带宽与慢速阶段的稳定性相结合。

公开(公告)号：US5157276A

公开(公告)日：1992-10-20

申请号：US765785

申请日：1991-09-26

申请人： Arthur J. Metz

发明人： Arthur J. Metz

IPC分类号： H03K5/13 ,  H03K5/135 ,  H03K17/62

CPC分类号： H03K17/6264

摘要： A low jitter clock phase adjust system divides an input clock signal into three clock signals having precisely equal phase differences from each other. The three clock signals are converted into current vectors and input to a trio of two-quadrature multipliers. The current vectors are multiplied by separate control signals generated from an input phase control signal. The separate control signals are generated such that only one of the separate control signals varies at a time. The result is a phase response output that is a linear function of the input phase control signal and that provides a phase adjustment range from -60.degree. to 360.degree..

公开(公告)号：US4916338A

公开(公告)日：1990-04-10

申请号：US282526

申请日：1988-12-12

申请人： Arthur J. Metz

发明人： Arthur J. Metz

IPC分类号： H03F3/45 ,  H03F3/50 ,  H03K5/02

CPC分类号： H03F3/505 ,  H03F3/45085 ,  H03K5/023 ,  H03F2203/45592 ,  H03F2203/45594

摘要： An FET buffer amplifier circuit includes two matched FET amplifiers each consisting of an FET transistor source follower biased by a source impedance. One FET transistor source follower receives an input voltage and the second FET transistor source follower is driven by the output of an operational amplifier. The positive and negative inputs of the operational amplifier are respectively coupled to the outputs of each FET transistor source follower. A negative feedback loop is created in which the output voltage of the operational amplifier is equal to the input voltage. The two FET transistors and source impedances are matched and are under substantially identical operating conditions.

摘要翻译： FET缓冲放大器电路包括两个匹配的FET放大器，每个FET放大器由一个源极阻抗偏置的FET晶体管源极跟随器组成。 一个FET晶体管源极跟随器接收输入电压，并且第二FET晶体管源极跟随器由运算放大器的输出驱动。 运算放大器的正和负输入分别耦合到每个FET晶体管源极跟随器的输出。 产生负反馈环路，其中运算放大器的输出电压等于输入电压。 两个FET晶体管和源极阻抗匹配，并且处于基本相同的工作条件下。

公开(公告)号：US4801827A

公开(公告)日：1989-01-31

申请号：US115785

申请日：1987-11-02

申请人： Arthur J. Metz

发明人： Arthur J. Metz

IPC分类号： H03K5/04 ,  H03K5/00 ,  H03K5/13 ,  H03K19/003 ,  H03K5/159

CPC分类号： H03K5/13 ,  H03K19/00323 ,  H03K2005/00052 ,  H03K2005/00176 ,  H03K2005/00182 ,  H03K2005/00228

摘要： An adjustable delay element for digital systems includes a high-pass filter in parallel with a low-pass filter. The high-pass filter passes the higher frequency component of the digital signal and the low-pass filter passes the lower frequency component to introduce a delay into the digital signal. A current multiplier directs a selectable portion of the higher frequency component to aid or oppose the lower frequency component to vary the delay within the signal. An output stage receives the lower frequency component with the selected portion of the higher frequency component and reproduces the digital signal with the delay. Embodiments for both differential and single-ended versions of the corresponding delay element are disclosed.

公开(公告)号：US4755766A

公开(公告)日：1988-07-05

申请号：US41382

申请日：1987-04-22

申请人： Arthur J. Metz

发明人： Arthur J. Metz

IPC分类号： H03F1/30 ,  H03F1/32 ,  H03F3/45

CPC分类号： H03F3/45197 ,  H03F3/45098

摘要： A differential to a single-ended converter circuit includes linearizing PN junctions that compensate for input signal voltage loss in the input stage. A variable voltage source and a resistor are provided for adjusting the voltage produced across these junctions by varying the current through these junctions. The converter circuit also includes a shunt feedback amplifier for inverting half the differential output voltage so that it sums with the differential voltage of opposite phase to produce the single-ended output signal. The shunt feedback amplifier is operated at a constant current to minimize error voltages. Bootstrapping is employed to linearize thermal distortion of the PN junctions and means are provided for compensating for the resulting thermal distortion.

公开(公告)号：US4705961A

公开(公告)日：1987-11-10

申请号：US820590

申请日：1986-01-21

申请人： Walter W. Ainsworth ,  Arthur J. Metz

发明人： Walter W. Ainsworth ,  Arthur J. Metz

IPC分类号： H03K4/502 ,  H03K4/08 ,  H03K4/84

CPC分类号： H03K4/502

摘要： A programmable sweep generator for generating a linear ramp signal of different slopes in a predetermined step sequence is disclosed. The programmable sweep generator comprises a controllable voltage generator, a voltage-to-current converter, and integrator sections. The slopes of the ramp signal may be electronically controlled by switching the controllable voltage generator, voltage-to-current converter and timing capacitors in the integrator section. The use of independent buffer amplifiers, independent control circuits, and current steering devices for each timing capacitor eliminates the need to connect a switching element in series with each timing capacitor, thereby eliminating any error or non-linearity.

摘要翻译： 公开了一种用于以预定步骤序列产生不同斜率的线性斜坡信号的可编程扫描发生器。 可编程扫描发生器包括可控电压发生器，电压 - 电流转换器和积分器部分。 可以通过在积分器部分中切换可控电压发生器，电压 - 电流转换器和定时电容器来电子控制斜坡信号的斜率。 对于每个定时电容器使用独立的缓冲放大器，独立控制电路和电流转向装置消除了将开关元件与每个定时电容器串联的需要，从而消除任何错误或非线性。

公开(公告)号：US4663610A

公开(公告)日：1987-05-05

申请号：US801118

申请日：1985-11-22

申请人： Arthur J. Metz ,  James S. Lamb

发明人： Arthur J. Metz ,  James S. Lamb

IPC分类号： H03M1/08 ,  H03M1/00 ,  H03M1/66 ,  H03M1/74

CPC分类号： H03M1/745

摘要： A serial DAC comprises two shift registers having their data input terminals connected together for receiving serial binary data. The shift registers are clocked alternately, whereby each shift register is clocked at substantially half the rate at which data is applied to the data input terminals of the shift registers. Two current switches are associated with the shift registers respectively, each switch being operative to steer input current to one of two output terminals if the data output of the associated shift register is a digital 1 and to steer input current to the other output terminal if the data output is a digital 0. Two current sources supply equal, constant currents to input terminals of the two current switches respectively. A third current switch has two output terminals connected to the input terminals of the first and second switches respectively, and is operative to steer its input current to its two output terminals in alternating fashion, switching between its two output terminals at the same rate as the shift registers are clocked. A third constant current source supplies the third switch with an input current equal to that supplied by the first and second sources, and the current supplied by the third current source is added alternately to the current supplied by the first source and the current supplied by the second source.

摘要翻译： 串行DAC包括两个移位寄存器，其数据输入端连接在一起用于接收串行二进制数据。 移位寄存器交替地进行时钟输入，由此每个移位寄存器的时钟基本上是将数据施加到移位寄存器的数据输入端的速率的一半。 两个电流开关分别与移位寄存器相关联，如果相关联的移位寄存器的数据输出是数字1，则每个开关可操作以将输入电流转向两个输出端中的一个，并且如果输入电流 数据输出为数字0.两个电流源分别为两个电流开关的输入端提供相等的恒定电流。 第三电流开关具有分别连接到第一和第二开关的输入端子的两个输出端子，并且可操作地以其交替方式将其输入电流转向其两个输出端子，以与其相同的速率在其两个输出端子之间切换 移位寄存器是时钟。 第三恒流源向第三开关提供等于由第一和第二源提供的输入电流的输入电流，并且将由第三电流源提供的电流交替地添加到由第一源提供的电流和由第一源提供的电流 第二来源。

公开(公告)号：US4551656A

公开(公告)日：1985-11-05

申请号：US437971

申请日：1982-11-01

申请人： Arthur J. Metz

发明人： Arthur J. Metz

IPC分类号： G01R13/24 ,  G01R13/28 ,  G01R13/32

CPC分类号： G01R13/24 ,  G01R13/28 ,  G01R13/32

摘要： An oscilloscope is provided with a dual time base system in which the nonlinear startup segment of the main sweep is eliminated before delay time comparison, thereby facilitating accurate differential measurements down to and including the triggering event (zero time). System delays are built in to ensure that the displayed sweep trace also begins at the left edge of the viewing screen, and, moreover, the triggering event may be viewed on both the main and delayed sweeps. The built-in system delays may be programmable to facilitate delay matching of vertical channels or time matching of independent sweep operation.

摘要翻译： 示波器具有双时基系统，其中在延迟时间比较之前消除了主扫描的非线性启动段，从而有助于精确的差分测量，直到并包括触发事件（零时间）。 内置系统延迟以确保显示的扫描轨迹也从观察屏幕的左边缘开始，此外，可以在主扫描和延迟扫描两者之间查看触发事件。 内置的系统延迟可以是可编程的，以便于垂直信道的延迟匹配或独立扫描操作的时间匹配。