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    DATA COMMUNICATION METHOD, MEMORY POOLING SWITCH DEVICE, CLOUD COMPUTING SYSTEM, AND STORAGE MEDIUM
    1.
    发明申请
    DATA COMMUNICATION METHOD, MEMORY POOLING SWITCH DEVICE, CLOUD COMPUTING SYSTEM, AND STORAGE MEDIUM 有权

    公开(公告)号：US20250068748A1

    公开(公告)日：2025-02-27

    申请号：US18812988

    申请日：2024-08-22

    Applicant: Alibaba Innovation Private Limited

    Inventor： Tianchan GUAN ,  Yijin GUAN ,  Zhaoyang DU ,  Dimin NIU

    IPC: G06F21/60 ,  G06F13/42

    Abstract: The embodiments of the present invention provide a data communication method, a memory pooling switch device, a cloud computing system, and a storage medium. The data communication method comprises: converting verification preprocessed memory data from a receiver's communication protocol format to a sender's communication protocol format, wherein the receiver's communication protocol format and the sender's communication protocol format are used for asymmetric communication protocols on a communication bus between a server and a memory pooling switch device; performing verification processing on the verification preprocessed memory data to obtain a verification result; transmitting the verification result to the server via the communication bus in the sender's communication protocol format.

    PHYSICAL HOST, OPERATION METHOD OF PHYSICAL HOST, AND COMPUTER-READABLE STORAGE MEDIUM FOR EXECUTING OPERATION METHOD
    4.
    发明申请
    PHYSICAL HOST, OPERATION METHOD OF PHYSICAL HOST, AND COMPUTER-READABLE STORAGE MEDIUM FOR EXECUTING OPERATION METHOD 有权

    公开(公告)号：US20240370168A1

    公开(公告)日：2024-11-07

    申请号：US18654494

    申请日：2024-05-03

    Applicant: Alibaba Innovation Private Limited

    Inventor： Jiacheng MA ,  Tianchan GUAN ,  Yijin GUAN ,  Dimin NIU ,  Hongzhong ZHENG

    IPC: G06F3/06

    Abstract: The present disclosure provides a physical host including a memory, a first buffer, a second buffer, a third buffer and a processor. The first buffer stores a log regarding a plurality of dirty pages. The second buffer stores a dirty bitmap, where the dirty bitmap is written into the second buffer according to the log read from the first buffer. The third buffer stores the dirty bitmap. The processor obtains the current memory address to be migrated and a destination memory address, and marks a page table corresponding to the memory address to be migrated as a plurality of dirty pages and writes the log marked as the plurality of dirty pages into the first buffer when the memory address to be migrated is written. The processor includes a memory copy engine for reading the dirty bitmap from the third buffer, and copying the content corresponding to the plurality of dirty pages to the destination memory according to the dirty bitmap.

    Temporal merge candidates in merge candidate lists in video coding
    5.
    发明授权
    Temporal merge candidates in merge candidate lists in video coding 有权

    公开(公告)号：US12137208B2

    公开(公告)日：2024-11-05

    申请号：US17955525

    申请日：2022-09-28

    Applicant: Alibaba Innovation Private Limited

    Inventor： Ru-Ling Liao ,  Jie Chen ,  Yan Ye ,  Xinwei Li

    IPC: H04N19/105 ,  H04N19/139 ,  H04N19/172

    Abstract: A VVC-standard encoder and a VVC-standard decoder implement improvements over VVC and ECM in a number of regards: a temporal motion vector prediction candidate selection method utilizing relocation of a collocated CTU; a temporal motion vector prediction candidate selection method utilizing expanded selection range; a temporal motion vector prediction candidate selection method utilizing unconditional derivation of a scaled motion vector; a temporal motion vector prediction candidate selection method utilizing omission of scaling uni-predicted motion vectors to bi-predicted motion vectors; a temporal motion vector prediction candidate selection method utilizing multiple options in setting a reference picture index; a temporal motion vector prediction candidate selection method utilizing scaling factor offsetting; a merge candidate list building method omitting a temporal motion vector prediction candidate; and a picture reconstruction method utilizing motion information refinement.

    SYSTEM ON CHIP AND INTERRUPT ISOLATION METHOD
    6.
    发明公开
    SYSTEM ON CHIP AND INTERRUPT ISOLATION METHOD 审中-公开

    公开(公告)号：US20240362175A1

    公开(公告)日：2024-10-31

    申请号：US18645904

    申请日：2024-04-25

    Applicant: Alibaba Innovation Private Limited

    Inventor： Zhixing CHEN ,  Wenbin ZHENG

    IPC: G06F13/24

    CPC classification number: G06F13/24

    Abstract: A system on chip includes an interrupt controller, a processor, and an on-chip bus, wherein the interrupt controller is connected to the processor through the on-chip bus. The interrupt controller is configured to store execution environment identifiers corresponding to different execution environments; and send, after receiving a first interrupt instruction, the first interrupt instruction to the processor. The processor is configured to obtain, in response to the first interrupt instruction, a first execution environment identifier corresponding to the first interrupt instruction from the interrupt controller; and execute, when the first execution environment identifier is the same as a second execution environment identifier, the first interrupt instruction in a corresponding execution domain of a current execution environment, wherein the second execution environment identifier is an execution environment identifier of an execution environment to which a current execution domain belongs.

    METHODS AND NON-TRANSITORY COMPUTER READABLE STORAGE MEDIUM FOR SPATIAL RESAMPLING TOWARDS MACHINE VISION
    8.
    发明公开
    METHODS AND NON-TRANSITORY COMPUTER READABLE STORAGE MEDIUM FOR SPATIAL RESAMPLING TOWARDS MACHINE VISION 审中-公开

    公开(公告)号：US20240357118A1

    公开(公告)日：2024-10-24

    申请号：US18618551

    申请日：2024-03-27

    Applicant: Alibaba Innovation Private Limited

    Inventor： Shurun WANG ,  Yan YE

    IPC: H04N19/132 ,  H04N19/172 ,  H04N19/186 ,  H04N19/436

    CPC classification number: H04N19/132 ,  H04N19/172 ,  H04N19/186 ,  H04N19/436

    Abstract: A method of encoding a video sequence into a bitstream. The method includes receiving a video sequence; performing a plurality of convolutions on an input image data of the video sequence in YUV format; wherein performing the plurality of convolutions includes performing a first stage convolution on the input image data, wherein the first stage convolution comprises a first convolution and a second convolution that are provided in parallel; performing a second stage convolution on a channel-wise concatenation result of an output of the first convolution and an output of the second convolution; performing a third stage convolution on an output of the second stage convolution; and obtaining an output image data based on an output of the third stage convolution; and encoding the output image data for generating the bitstream.

    SWITCH, MEMORY SHARING METHOD, SYSTEM, COMPUTING DEVICE, AND STORAGE MEDIUM
    10.
    发明申请
    SWITCH, MEMORY SHARING METHOD, SYSTEM, COMPUTING DEVICE, AND STORAGE MEDIUM 有权

    公开(公告)号：US20250068577A1

    公开(公告)日：2025-02-27

    申请号：US18812672

    申请日：2024-08-22

    Applicant: Alibaba Innovation Private Limited

    Inventor： Yijin GUAN ,  Dimin NIU ,  Tianchan GUAN ,  Zhaoyang DU ,  Hongzhong ZHENG

    IPC: G06F13/40 ,  G06F13/16 ,  G06F13/42

    Abstract: The present invention provides a switch, which is equipped with multiple connection interfaces, for connecting to multiple external processors respectively, enabling mutual access to the respective memories of these processors through the switch. The switch is configured to: through a memory request service component corresponding to a first processor, set within the switch, receive a first memory request sent by the first processor; convert the first memory request into a second memory request aimed at accessing the memory of a second processor and send this second memory request to a memory response service component corresponding to the second processor within the switch; through the memory response service component, convert the second memory request into a third memory request for accessing local memory and send this third memory request to the second processor to access the memory resources corresponding to the second processor.

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