公开(公告)号：US06275519B1

公开(公告)日：2001-08-14

申请号：US09148268

申请日：1998-09-04

申请人： Alan F. Hendrickson

发明人： Alan F. Hendrickson

IPC分类号： A61F206

CPC分类号： H04L1/24 ,  H04L7/0054 ,  H04L7/0334

摘要： In a digital communication receiver, a system and method for recovering the timing of frames in the received signal. The receiver synchronizes an internal frame clock with a series of received data frames in the received data stream. One embodiment of a method for performing the frame synchronization proceeds by first recovering a symbol timing for data symbols in the received frames, then acquiring a frame timing by scanning the received data symbols for the SYNC field only during a narrow detection window around an expected location in time for the SYNC field, and then locking the frame timing. An embodiment of a system for performing the frame synchronization comprises an input for receiving the data frames in the received data stream, a symbol clock that indicates symbol transitions in the received data stream, timing logic that indicates the detection window during which the a SYNC field is expected, a SYNC-field detector, and a receiver frame clock.

摘要翻译： 一种数字通信接收机，用于恢复接收信号中帧的定时的系统和方法。 接收器将内部帧时钟与接收到的数据流中的一系列接收到的数据帧进行同步。 用于执行帧同步的方法的一个实施例是通过首先恢复接收到的帧中的数据符号的符号定时来进行，然后仅在预期位置周围的窄检测窗口期间扫描SYNC字段的接收数据符号来获取帧定时 及时为SYNC字段，然后锁定帧定时。 用于执行帧同步的系统的实施例包括用于接收接收数据流中的数据帧的输入，指示接收到的数据流中的符号转换的符号时钟，指示检测窗口的定时逻辑，在该时间逻辑期间，SYNC字段 期望的是SYNC场检测器和接收机帧时钟。

公开(公告)号：US06256337B1

公开(公告)日：2001-07-03

申请号：US09148607

申请日：1998-09-04

申请人： Alan F. Hendrickson ,  Ken M. Tallo

发明人： Alan F. Hendrickson ,  Ken M. Tallo

IPC分类号： H04L2730

CPC分类号： H04L1/24 ,  H04L7/0054 ,  H04L7/0334

摘要： In a direct sequence spread spectrum communication system, a system and method for recovering the timing of a pseudo-random noise (PN) sequence used for despreading the received signals. In one embodiment, the communication system is a time-division duplexing (TDD) or a time-division multiple-access (TDMA) system. A receiver in the communication system uses a “sliding correlator” maximal-likelihood (ML) detection system to scan through a range of possible PN phases to determine the correct one. In one embodiment of a method for performing the synchronization, a receiver acquires the PN phase by repeating the ML detection for a time greater than or equal to the period of the TDD or TDMA frames, with a sufficiently high repetition rate to ensure that the correct PN phase is examined at least once during a received frame. The acquisition is thereby completed within a fixed amount of time. One embodiment of a system for performing the synchronization includes an input for the received signal, a receiver PN clock, and an ML detection logic. The ML detection logic repeats the ML detection so that at least one complete set of PN phases is examined during a time when the received signal is active. In another embodiment of the method, the receiver acquires the PN phase by performing the ML detection during a timeslot in which a received frame is expected. Again, the acquisition is completed within a fixed amount of time.

摘要翻译： 在直接序列扩频通信系统中，用于恢复用于解扩接收信号的伪随机噪声（PN）序列的定时的系统和方法。 在一个实施例中，通信系统是时分双工（TDD）或时分多址（TDMA）系统。 通信系统中的接收机使用“滑动相关器”最大似然（ML）检测系统来扫描可能的PN相的范围以确定正确的PN相位。 在用于执行同步的方法的一个实施例中，接收机通过以足够高的重复率重复ML检测大于或等于TDD或TDMA帧的周期的时间来获取PN相位，以确保正确的 PN帧在接收帧期间至少检查一次。 因此，在一段固定的时间内完成收购。 用于执行同步的系统的一个实施例包括用于接收信号的输入，接收机PN时钟和ML检测逻辑。 ML检测逻辑重复ML检测，使得在接收信号有效的时间期间检查至少一个完整的PN相组。 在该方法的另一实施例中，接收机通过在期望接收帧的时隙中执行ML检测来获取PN相位。 同样，收购在固定的时间内完成。

公开(公告)号：US5940435A

公开(公告)日：1999-08-17

申请号：US78145

申请日：1998-05-13

申请人： Alan F. Hendrickson

发明人： Alan F. Hendrickson

IPC分类号： H04L1/24 ,  H04L7/02 ,  H04L7/033 ,  H04B15/00 ,  H04K1/00 ,  H04L27/14 ,  H04L27/30

CPC分类号： H04L1/24 ,  H04L7/0054 ,  H04L7/0334

摘要： A method for configuring the receiver with an IF delay value that indicates the timing of symbol transitions in a received signal processed by the receiver. The receiver recovers a timing that has the same period as the symbol period, but which is out of phase with the received symbols. The received symbols are members of a constellation with elements that have purely I or purely Q components. A symbol-quality signal is generated by constructing the quantity .vertline..vertline.I.vertline.-.vertline.Q.vertline..vertline.. This quantity is a maximum when the detected symbols are aligned with the expected points in the symbol constellation, and decreases if the detected symbols are rotated away from these constellation points. The method determines an optimal delay value by which the symbol clock should be shifted from the recovered timing by using the symbol-quality signal to evaluate test delays and to successively refine them until the optimal delay value is found.

摘要翻译： 一种用于配置具有IF延迟值的接收机的方法，所述IF延迟值指示由接收机处理的接收信号中的符号转换的定时。 接收机恢复与符号周期具有相同周期但与接收到的符号不同步的定时。 所接收的符号是具有纯I或纯Q分量的元素的星座的成员。 通过构造量|| I | - | Q ||生成符号质量信号。 当检测到的符号与符号星座中的预期点对准时，该量是最大值，如果检测到的符号从这些星座点旋转，则该量减小。 该方法通过使用符号质量信号来评估测试延迟并且连续细化它们直到找到最佳延迟值来确定符号时钟应该从恢复的定时偏移的最佳延迟值。

公开(公告)号：US5900749A

公开(公告)日：1999-05-04

申请号：US856358

申请日：1997-05-14

申请人： Alan F. Hendrickson ,  Peter E. Sheldon

发明人： Alan F. Hendrickson ,  Peter E. Sheldon

IPC分类号： H03K5/08 ,  H04L25/06 ,  H03K5/00 ,  H03K25/06

CPC分类号： H04L25/065 ,  H03K5/082 ,  H04L25/062

摘要： A circuit for generating a threshold voltage level from a time division duplex analog data signal. The circuit comprises a sample/hold circuit and an amplifier. The sample/hold circuit is arranged to sample the threshold voltage level during a reception interval and hold the threshold voltage level during a transmission interval. The amplifier includes an operational amplifier coupled to the sample/hold circuit for amplifying the analog data signal during a reception interval and amplifying the threshold voltage level during a transmission interval. A transconductance device is coupled to the operational amplifier, and a plurality of load legs are respectively coupled to a plurality of bias legs. A first selected pair of the respectively coupled load legs and bias legs is coupled to the transconductance device, and a second selected pair of the respectively coupled load legs and bias legs coupled to the output of the amplifier to provide the threshold voltage level.

摘要翻译： 一种用于从时分双工模拟数据信号产生阈值电压电平的电路。 电路包括采样/保持电路和放大器。 采样/保持电路被布置成在接收间隔期间对门限电压电平进行采样，并在发送间隔期间保持阈值电压电平。 放大器包括耦合到采样/保持电路的运算放大器，用于在接收间隔期间放大模拟数据信号，并在发送间隔期间放大阈值电压电平。 跨导装置耦合到运算放大器，并且多个负载支路分别耦合到多个偏置支路。 分别耦合的负载支路和偏置支路的第一选择的一对耦合到跨导装置，以及耦合到放大器的输出端的分别耦合的负载支路和偏置支路的第二选定对，以提供阈值电压电平。

公开(公告)号：US5839061A

公开(公告)日：1998-11-17

申请号：US531049

申请日：1995-09-20

申请人： Alan F. Hendrickson ,  Joseph W. Peterson

发明人： Alan F. Hendrickson ,  Joseph W. Peterson

IPC分类号： H04B1/10 ,  H04B7/08 ,  H04B17/00

CPC分类号： H04B1/1027 ,  H04B17/318 ,  H04B7/08

摘要： A communication circuit designed to be coupled to a radio receiver so as to receive a data signal and a receive signal strength indicator signal indicative of radio carrier strength therefrom, and further designed to be coupled to a controller, the communications circuit including a first, second, third, and fourth subcircuit. The first subcircuit receives the receive signal strength indicator from the receiver, determines radio carrier strength therefrom, and transfers the determined strength information to the controller. The second subcircuit receives the data signal from the receiver, determines if there are bit error within that signal, and transfers its determinations to the controller. The third subcircuit receives the data signal from the receiver, determines if there is jitter therein, and transfers its determinations to the controller. The fourth subcircuit is coupled to the second and third subcircuits to receive the output thereof, and is further coupled to the controller so as to receive output therefrom, the fourth subcircuit acting in response to the outputs to suppress signal noise.

摘要翻译： 一种通信电路，被设计为耦合到无线电接收机，以便从其接收指示无线电载波强度的数据信号和接收信号强度指示符信号，并进一步设计为耦合到控制器，所述通信电路包括第一，第二 ，第三和第四分支电路。 第一子电路从接收器接收接收信号强度指示符，从其确定无线电载波强度，并将确定的强度信息传送到控制器。 第二分支电路接收来自接收机的数据信号，确定该信号内是否存在位错误，并将其确定传送给控制器。 第三分支电路接收来自接收机的数据信号，确定其中是否存在抖动，并将其确定传送给控制器。 第四子电路耦合到第二和第三子电路以接收其输出，并且还耦合到控制器，以便从其接收输出，第四子电路响应于输出而起作用以抑制信号噪声。

公开(公告)号：US5697062A

公开(公告)日：1997-12-09

申请号：US191818

申请日：1994-02-04

申请人： Alan F. Hendrickson

发明人： Alan F. Hendrickson

IPC分类号： H04L29/08 ,  H04L7/10 ,  H04M1/725 ,  H04Q7/38 ,  H04B7/26

CPC分类号： H04M1/72505 ,  H04L7/10

摘要： A method and apparatus for radio frequency (RF) link establishment is disclosed. The method and apparatus uses messages with a set data field containing N-bit channel markers and synchronization words for link establishment and monitoring. The present invention allows for correct detection of the initial channel marker even if less than N bits are received correctly.

摘要翻译： 公开了射频（RF）链路建立的方法和装置。 该方法和装置使用具有包含N位信道标记的设置数据字段和用于链路建立和监视的同步字的消息。 本发明允许正确地检测初始信道标记，即使正确地接收到少于N个比特。

公开(公告)号：US5596724A

公开(公告)日：1997-01-21

申请号：US191948

申请日：1994-02-04

申请人： Jacqueline Mullins ,  Joseph W. Peterson ,  John Bartkowiak ,  Alan F. Hendrickson

发明人： Jacqueline Mullins ,  Joseph W. Peterson ,  John Bartkowiak ,  Alan F. Hendrickson

IPC分类号： G06F13/38 ,  G06F5/00 ,  H03M9/00

CPC分类号： H03M9/00

摘要： The present invention disclosed an input/output data port circuit which connects a parallel data bus with an input serial data bus and an output serial data bus. The input/output data port is selectively operable in either a linear mode or a buffered mode. The input/output port is comprised of an interface register that is connected to a parallel data bus, a serial input bus and a serial output bus; a temporary register that is serially connected to the interface register, an outbound register that is connected in parallel to the temporary register and serially connected to a serial bus; and an inbound register that is connected in parallel to the temporary register and serially connected to a serial, bus.

摘要翻译： 本发明公开了一种将并行数据总线与输入串行数据总线和输出串行数据总线连接的输入/输出数据端口电路。 输入/输出数据端口可选择性地以线性模式或缓冲模式工作。 输入/输出端口包括连接到并行数据总线，串行输入总线和串行输出总线的接口寄存器; 串行连接到接口寄存器的临时寄存器，与临时寄存器并联并串行连接到串行总线的出站寄存器; 以及与临时寄存器并行连接并串行连接到串行总线的入站寄存器。

公开(公告)号：US5404459A

公开(公告)日：1995-04-04

申请号：US918624

申请日：1992-07-21

申请人： Dale E. Gulick ,  Alan F. Hendrickson ,  Munehiro Yoshikawa ,  Hiroshi Matsubara ,  Kazushige Tsurumi

发明人： Dale E. Gulick ,  Alan F. Hendrickson ,  Munehiro Yoshikawa ,  Hiroshi Matsubara ,  Kazushige Tsurumi

IPC分类号： G06F15/78 ,  G06F1/04 ,  G06F13/42 ,  G06F1/32

CPC分类号： G06F13/423 ,  G06F1/04

摘要： A serial communication port structure for starting and stopping an internal clock. This internal clock is designed, in operation, to generate a clock output signal to be transmitted to a device external to the system in which the serial communication port is incorporated. By ANDing the clock output signal with a data output signal of predetermined length, the serial communication port can effectively control the passage of time as sensed by the external device.

摘要翻译： 用于启动和停止内部时钟的串行通信端口结构。 该内部时钟在工作时被设计为产生时钟输出信号，以将其发送到并入串行通信端口的系统外部的设备。 通过将时钟输出信号与预定长度的数据输出信号进行AND操作，串行通信端口可以有效地控制由外部设备感测到的时间的流逝。

公开(公告)号：US5134658A

公开(公告)日：1992-07-28

申请号：US589315

申请日：1990-09-27

申请人： Herbert M. Chen ,  Alan F. Hendrickson

发明人： Herbert M. Chen ,  Alan F. Hendrickson

IPC分类号： H04M1/60 ,  H04M9/08

CPC分类号： H04M9/085

摘要： The preferred embodiment of the apparatus comprises a first signal level detector which receives the communications signal as an input and generates a detection signal as an output, a second signal level detector which receives the detection signal as an input and generates a noise detection signal as an output, and a comparing circuit which compares the detection signal and the noise detection signal and produces a speech burst detection signal. Each of the signal level detectors comprises a digital low pass filter having an input and an output which employs a comparator for comparing current samples of signals at the input with previous samples of signals at the output and generating a representative comparator output. Each low pass filter includes circuitry for establishing an attack time and a decay time, in response to the comparator output. The attack time and the decay time in the first signal level detector being established as a fast attack time and a slow decay time relative to the attack time and the decay time in the second signal level detector.

公开(公告)号：US09036091B2

公开(公告)日：2015-05-19

申请号：US12986053

申请日：2011-01-06

申请人： Alan F. Hendrickson ,  Alessandro Piovaccari ,  Ramin Khoini-Poorfard ,  Mitchell Reid ,  Frederick Alan Rush ,  Jean-Marc Guyot ,  David Le Goff ,  Michael Robert May ,  Henry William Singor ,  Qi Cai ,  Peter Jozef Vancorenland ,  Chunyu Xin ,  Pascal Blouin

发明人： Alan F. Hendrickson ,  Alessandro Piovaccari ,  Ramin Khoini-Poorfard ,  Mitchell Reid ,  Frederick Alan Rush ,  Jean-Marc Guyot ,  David Le Goff ,  Michael Robert May ,  Henry William Singor ,  Qi Cai ,  Peter Jozef Vancorenland ,  Chunyu Xin ,  Pascal Blouin

IPC分类号： H04N5/44 ,  H04N5/50 ,  H04N21/426 ,  H04N5/46 ,  H03J1/00

CPC分类号： H04N21/42638 ,  H03J1/0008 ,  H04N5/46

摘要： An integrated circuit includes a tuner, a digital television (DTV) demodulator, an analog television (ATV) demodulator, and a controller. The tuner includes an input for receiving a radio frequency (RF) signal including at least one of an analog television signal and digital television signal, and including a first output terminal and a second output terminal. The DTV demodulator includes a DTV input coupled to the first output terminal of the tuner and includes a DTV output terminal. The ATV demodulator includes an ATV input coupled to the second output terminal of the tuner and includes an ATV output terminal. The controller is coupled to the tuner, the DTV demodulator, and the ATV demodulator to configure the tuner and at least one of the DTV demodulator and the ATV demodulator for receiving television content in a selected television format.

摘要翻译： 集成电路包括调谐器，数字电视（DTV）解调器，模拟电视（ATV）解调器和控制器。 调谐器包括用于接收包括模拟电视信号和数字电视信号中的至少一个的射频（RF）信号的输入，并且包括第一输出端和第二输出端。 DTV解调器包括耦合到调谐器的第一输出端的DTV输入，并且包括DTV输出端。 ATV解调器包括耦合到调谐器的第二输出端子的ATV输入并且包括ATV输出端子。 控制器耦合到调谐器，DTV解调器和ATV解调器，以配置调谐器和至少一个DTV解调器和ATV解调器，用于以选定的电视格式接收电视内容。