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    APPARATUS, SYSTEM AND METHOD OF DIRECT CURRENT (DC) ESTIMATION OF A WIRELESS COMMUNICATION PACKET
    2.
    发明申请
    APPARATUS, SYSTEM AND METHOD OF DIRECT CURRENT (DC) ESTIMATION OF A WIRELESS COMMUNICATION PACKET 有权
    无线通信分组的直流（DC）估计的装置，系统和方法

    公开(公告)号：US20140126390A1

    公开(公告)日：2014-05-08

    申请号：US13669587

    申请日：2012-11-06

    申请人： Moshe Teplitsky ,  Michael Genossar ,  Elan Banin

    发明人： Moshe Teplitsky ,  Michael Genossar ,  Elan Banin

    IPC分类号： H04W24/00

    CPC分类号： H04L25/062 ,  H04L25/065

    摘要： Some demonstrative embodiments include devices, systems and/or methods of Direct Current (DC) estimation. For example, an apparatus may include an estimator to estimate a DC component of a received wireless communication packet based on a first value, a second value and an estimated frequency offset, wherein the first value is based on a first plurality of samples including at least a plurality of samples of a first sequence of a preamble of the wireless communication packet, the second value is based on a second plurality of samples including at least a plurality of samples of a second sequence of the preamble, immediately successive to the first sequence, and the estimated frequency offset corresponds to a frequency offset between the first and second pluralities of samples.

    摘要翻译： 一些演示实施例包括直流（DC）估计的装置，系统和/或方法。 例如，装置可以包括估计器，用于基于第一值，第二值和估计的频率偏移来估计接收到的无线通信分组的DC分量，其中第一值基于至少包括第一多个样本 所述无线通信分组的前导码的第一序列的多个样本，所述第二值基于包括所述前导码的第二序列的至少多个采样的第二多个采样，所述第二序列紧接着所述第一序列， 并且估计的频率偏移对应于第一和第二多个样本之间的频率偏移。

    Control arrangements for digital radio receivers
    3.
    发明授权
    Control arrangements for digital radio receivers 失效
    数字无线电接收机的控制装置

    公开(公告)号：US5663989A

    公开(公告)日：1997-09-02

    申请号：US324910

    申请日：1994-10-18

    申请人： Ian Godfrey Fobbester

    发明人： Ian Godfrey Fobbester

    IPC分类号： H03J7/02 ,  H03J7/04 ,  H04B1/26 ,  H04L7/04 ,  H04L27/14 ,  H04L27/148 ,  H04L27/152 ,  H04L27/06

    CPC分类号： H04L25/065 ,  H03J7/02 ,  H03J7/04 ,  H04B1/26 ,  H04L27/142 ,  H04L27/148 ,  H04L27/1525 ,  H04L7/046

    摘要： In a frequency modulated digital radio transmission system, frequency differences between transmitter and receiver which give rise to DC offsets at the output of the demodulator are countered for any one data transmission by establishing a frequency controlling or DC level controlling signal during a preamble sequence having a known constant DC component, such as the sequence 10101 - - - used for clock or data synchronization, and retaining that controlling signal substantially unaltered for use during the remainder of that data transmission.

    摘要翻译： 在频率调制的数字无线电传输系统中，通过在具有频率调制数字无线电传输系统的前导码序列期间建立频率控制或DC电平控制信号来对通过解调器输出端产生DC偏移的发射机和接收机之间的频率差进行抵消， 已知的恒定DC分量，例如用于时钟或数据同步的序列10101 - - ，并且在该数据传输的剩余期间保持该控制信号基本上不改变以供使用。

    Adaptive limiter/detector which changes time constant upon detection of dotting pattern
    5.
    发明授权
    Adaptive limiter/detector which changes time constant upon detection of dotting pattern 失效
    自适应限制器/检测器，在检测到点阵图案时改变时间常数

    公开(公告)号：US4821292A

    公开(公告)日：1989-04-11

    申请号：US56924

    申请日：1987-06-03

    申请人： Jeffrey S. Childress

    发明人： Jeffrey S. Childress

    IPC分类号： H04L7/04 ,  H04L25/06 ,  H04W84/08

    CPC分类号： H04W84/08 ,  H04L25/061 ,  H04L25/063 ,  H04L25/065 ,  H04L7/046

    摘要： A limiter/detector which takes advantage of the characteristics of the dotting pattern preceding each message in the General Electric Public Service Trunking System shortens bit synchronization acquisition time and improves incoming signal detection. Since the lowest frequency component in the dotting pattern is 4800 Hz, the time constant of the receiver adaptive limiter is decreased from 0.1 seconds to 0.33 microseconds (corresponding to a cut-off frequency of 3 KHz) during the time a dotting pattern is (or might be) received. This decreased time constant allows the limiter to adapt much more rapidly to the DC component of the incoming data signal. Upon successful decoding of the dotting pattern preceding the message, the limiter circuit time constant is changed to 0.1 seconds to allow lower frequency digital data signal components (e.g., those lower frequency components associated with word sync patterns such as Barker codes) to be detected. The limiter provides the advantages of decreased falsing rate, more reliable detection of word sync, more rapid acquisition of bit sync, better utilization of processing resources, simplification of initial signal detection routines and/or circuitry, and more rapid adaptivity to incoming signalling.

    摘要翻译： 利用通用电气公共服务中继系统中每个消息之前的点号模式的特征的限制器/检测器缩短位同步采集时间并改善输入信号检测。 由于点号图案中的最低频率分量为4800Hz，所以在点阵图形为（或）时，接收机自适应限制器的时间常数从0.1秒降低到0.33微秒（对应于截止频率3KHz） 可能）。 这种减小的时间常数允许限幅器更快地适应输入数据信号的DC分量。 成功解码消息之前的点阵图案时，将限制器电路时间常数改变为0.1秒以允许检测低频数字数据信号分量（例如，与诸如巴克码之类的字同步模式相关联的那些较低频率分量）。 限幅器提供了降低伪造率，更可靠的字同步检测，更快速地获取位同步，更好地利用处理资源，简化初始信号检测程序和/或电路以及更快速地适应输入信令的优点。

    Optoelectric transducer
    6.
    发明授权
    Optoelectric transducer 失效
    光电传感器

    公开(公告)号：US4714828A

    公开(公告)日：1987-12-22

    申请号：US839719

    申请日：1986-03-14

    申请人： Claude Bacou ,  Rene Baptiste ,  Henri Feissel ,  Gilbert Takats ,  Christian Cabrol

    发明人： Claude Bacou ,  Rene Baptiste ,  Henri Feissel ,  Gilbert Takats ,  Christian Cabrol

    IPC分类号： H04B10/04 ,  H03G3/20 ,  H04B10/00 ,  H04B10/06 ,  H04B10/14 ,  H04B10/158 ,  H04B10/26 ,  H04B10/28 ,  H01J40/14

    CPC分类号： H04L25/065 ,  H03G3/3084 ,  H04B10/6931

    摘要： An optoelectronic transducer is proposed which includes a PIN diode (2) that delivers a current that is proportional to a light signal that is received. The diode is connected to the input of an inverting amplifier (4) that delivers a voltage signal v.sub.s. A negative feedback means of the transfer impedance type (6) is connected across the inverting amplifier. The transducer further includes a stabilizing means (8) for the amplifier gain and a temperature drift compensating means (10) for compensating for the drift in amplifier temperature. The stabilizing means (8) includes a detector (26, 28, 32) for the high peak of the signal v.sub.s, and the temperature drift compensating means (10) includes a filter means (38) for producing the means value v.sub.m of the signal v.sub.s, and a comparator (40) that receives the signals v.sub.s and v.sub.m and delivers a signal that reproduces the interference of the light signal that has been received. The temperature drift compensating (10) also includes a carrier wavedetection (cs) with automatic control (42). This automatic control enables very high speed detection of the carrier wave not only at a high level, but at a low level as well.

    摘要翻译： 提出了一种光电转换器，其包括输出与所接收的光信号成比例的电流的PIN二极管（2）。 二极管连接到反相放大器（4）的输入端，反相放大器（4）输出电压信号，而反相放大器连接的传输阻抗型（6）的负反馈装置。 换能器还包括用于放大器增益的稳定装置（8）和用于补偿放大器温度漂移的温度漂移补偿装置（10）。 稳定装置（8）包括用于信号的高峰值的检测器（26,28,32），温度漂移补偿装置（10）包括滤波器装置（38），用于产生信号的装置值vm 以及比较器（40），其接收信号vs和vm并传送再现已经接收到的光信号的干扰的信号。 温度漂移补偿（10）还包括具有自动控制（42）的载波波形检测（cs）。 这种自动控制使得载波的非常高速检测不仅在高水平，而且处于低水平。

    Digital signal processing circuit
    7.
    发明授权
    Digital signal processing circuit 失效
    数字信号处理电路

    公开(公告)号：US4425548A

    公开(公告)日：1984-01-10

    申请号：US300346

    申请日：1981-09-08

    申请人： Kouzou Kage

    发明人： Kouzou Kage

    IPC分类号： H04L25/03 ,  H03K5/08 ,  H04L25/06 ,  H03K13/32

    CPC分类号： H04L25/065 ,  H04L25/063

    摘要： A digital data signal is distorted by means of a low or high pass filter. Quantization of such a signal in accordance with extracted clock pulses will result in a high error rate if a fixed quantization level is utilized due to attenuated voltage swings and a low differential between the signal excursions and the quantization level. The present invention overcomes this problem by means of a shift register connected to an output of a quantization comparator which is clocked by the extracted clock pulses. A weighting circuit is connected between the shift register and one of the inputs of the comparator to suitably adjust the relative quantization level to compensate for the asymmetrical voltage swings caused by the filtering and thereby greatly reduce the data error rate.

    摘要翻译： 数字数据信号通过低通或高通滤波器失真。 根据提取的时钟脉冲对这样的信号的量化将导致如果由于衰减的电压摆动而使用固定的量化电平而导致高错误率，以及在信号偏移和量化电平之间的低差分。 本发明通过连接到由提取的时钟脉冲对时钟的量化比较器的输出的移位寄存器来克服这个问题。 一个加权电路连接在移位寄存器和比较器的一个输入端之间，以适当调整相对量化电平，以补偿由滤波引起的非对称电压摆幅，从而大大降低数据错误率。

    Reference voltage regulator in a radar receiver
    8.
    发明授权
    Reference voltage regulator in a radar receiver 失效
    雷达接收机中的参考电压调节器

    公开(公告)号：US3555547A

    公开(公告)日：1971-01-12

    申请号：US3555547D

    申请日：1967-10-11

    申请人： ERICSSON TELEFON AB L M

    发明人： ARVIDSSON ERIK RAGNAR

    IPC分类号： G01S7/28 ,  G01S7/292 ,  H04L25/06 ,  G01S9/02

    CPC分类号： H04L25/065 ,  G01S7/2806 ,  G01S7/2922 ,  H04L25/063

    摘要： IN A RADAR RECEIVER A REFERENCE VOLTAGE IS GENERATED TO PROVIDE A CLIP LEVEL FOR RECEIVED SIGNALS. THE SIGNALS WHICH EXCEED THE CLIP LEVEL ARE USED TO GENERATE A PULSE COUNT WHOSE VALUE IS A FUNCTION OF THE TIME DURATION OF PASSED SIGNALS DURING A PORTION OF THE PERIOD BETWEEN TWO RANGE PULSES TRANSMITTED BY THE RADAR TRANSMITTER. A POSITIVE OR NEGATIVE SIGNAL IS GENERATED IN ACCORDANCE WITH WHETHER OR NOT THE ACTUAL COUNT VALUE EXCEEDS A GIVEN COUNT VALUE DURING THE PERIOD. THE SIGNAL SO GENERATED IS INTEGRATED TO PROVIDE THE REFERENCE VOLTAGE FOR THE NEXT PERIOD.