公开(公告)号：US09531256B2

公开(公告)日：2016-12-27

申请号：US14095759

申请日：2013-12-03

Applicant: AVOGY, INC.

Inventor： Hemal N. Shah ,  Vinod Khosla

IPC: H02M7/06 ,  H02M1/42 ,  G05F3/26 ,  H02M7/217

CPC classification number: H02M1/4208 ,  G05F3/26 ,  H02M1/42 ,  H02M7/06 ,  H02M7/217 ,  Y02B70/126

Abstract: An electrical adapter can include a rectifying circuit configured to receive an AC power input, a power factor corrector (PFC) circuit coupled with an output of the rectifying circuit, and a capacitive component coupled with an output of the PFC circuit. The electrical adapter can further include a DC-DC converter circuit coupled with an output of the capacitive component and configured to provide a power output of the electrical adapter, and an impedance-measuring circuit coupled with the power output and configured to measure impedance of a cable connected to the power output. The DC-DC converter circuit can be configured to adjust power of the power output based on the measured impedance.

Abstract translation: 电适配器可以包括被配置为接收AC电力输入的整流电路，与整流电路的输出耦合的功率因数校正器（PFC）电路以及与PFC电路的输出耦合的电容分量。 电适配器还可以包括与电容性部件的输出耦合并被配置为提供电适配器的功率输出的DC-DC转换器电路，以及与功率输出耦合的阻抗测量电路，并配置成测量 电缆连接到电源输出。 DC-DC转换器电路可以被配置为基于测量的阻抗来调整功率输出的功率。

公开(公告)号：US20160241148A1

公开(公告)日：2016-08-18

申请号：US15042421

申请日：2016-02-12

Applicant: Avogy, Inc.

Inventor： Isik Kizilyalli ,  Dinesh Ramanathan ,  Rob Levine ,  Mikhail Guz

IPC: H02M3/335 ,  H05K5/02 ,  H02M7/00

CPC classification number: H05K5/0247 ,  H02M3/33523 ,  H02M2001/0025 ,  H02M2001/007

Abstract: A variable output power supply includes a power unit comprising a housing including an output port, one or more accessories disposed in the housing, and a controller disposed in the housing and in communication with the output port. The variable output power supply also includes a power cable. The controller is operable to modify operation of the output port in response, at least in part, to insertion of the power cable in the output port.

Abstract translation: 可变输出电源包括动力单元，其包括壳体，该壳体包括输出端口，设置在壳体中的一个或多个附件，以及布置在壳体中并与输出端口连通的控制器。 可变输出电源还包括电源线。 控制器可操作以至少部分地修改输出端口的操作以将电力电缆插入输出端口。

公开(公告)号：US20160190954A1

公开(公告)日：2016-06-30

申请号：US14983050

申请日：2015-12-29

Applicant: Avogy, Inc.

Inventor： Alberto Doronzo

IPC: H02M7/04

CPC classification number: H02M1/4258 ,  Y02B70/126 ,  Y02P80/112

Abstract: An AC-DC converter configured to convert an input AC signal to an output DC signal is disclosed. The AC-DC converter includes an inductor and first and second transistors, where the inductor and first and second transistors are connected in series with one another. The input AC signal is applied across the series connected inductor and first and second transistors, and the series connected inductor and first and second transistors is configured to generate a secondary AC signal based on the AC input signal. The AC-DC converter also includes a rectifier, configured to rectify a signal based on the secondary AC signal to generate a substantially DC output signal based on the AC input signal.

Abstract translation: 公开了一种被配置为将输入AC信号转换为输出DC信号的AC-DC转换器。 AC-DC转换器包括电感器和第一和第二晶体管，其中电感器和第一和第二晶体管彼此串联连接。 输入AC信号施加在串联连接的电感器和第一和第二晶体管上，串联的电感器和第一和第二晶体管被配置为基于AC输入信号产生次级AC信号。 AC-DC转换器还包括整流器，被配置为基于次级AC信号对信号进行整流，以基于AC输入信号产生基本上为DC的输出信号。

公开(公告)号：US20160072317A1

公开(公告)日：2016-03-10

申请号：US14479855

申请日：2014-09-08

Applicant: Avogy, Inc.

Inventor： Mikhail Guz ,  Antoin Russell

IPC: H02J7/00 ,  H02J1/14

CPC classification number: H02J7/0021 ,  H02J1/14 ,  H02J7/0052 ,  H02J7/007 ,  H02J2007/0062

Abstract: A method of operating a power adapter having multiple outputs includes setting an output priority for each of the multiple outputs and providing an output voltage at each of the multiple outputs. The method also includes measuring one or more operating parameters of the power adapter and determining that at least one of the one or more operating parameters are greater than a setpoint. The method further includes reducing the output voltage associated with at least one of the multiple output ports.

Abstract translation: 一种操作具有多个输出的电源适配器的方法包括设置多个输出中的每一个的输出优先级，并在多个输出中的每个输出端提供输出电压。 该方法还包括测量电源适配器的一个或多个操作参数，并确定一个或多个操作参数中的至少一个大于设定值。 该方法还包括减少与多个输出端口中的至少一个相关联的输出电压。

公开(公告)号：US09171751B2

公开(公告)日：2015-10-27

申请号：US14264998

申请日：2014-04-29

Applicant: AVOGY, INC.

Inventor： Donald R. Disney ,  Andrew P. Edwards ,  Hui Nie ,  Richard J. Brown ,  Isik C. Kizilyalli ,  David P. Bour ,  Linda Romano ,  Thomas R. Prunty

IPC: H01L29/06 ,  H01L21/761 ,  H01L21/266 ,  H01L21/265 ,  H01L29/20 ,  H01L29/40 ,  H01L29/66 ,  H01L29/808 ,  H01L29/872

CPC classification number: H01L21/761 ,  H01L21/2654 ,  H01L21/266 ,  H01L21/765 ,  H01L29/0619 ,  H01L29/0642 ,  H01L29/0692 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/66136 ,  H01L29/66212 ,  H01L29/6631 ,  H01L29/66909 ,  H01L29/8083 ,  H01L29/872

Abstract: A method for fabricating an edge termination structure includes providing a substrate having a first surface and a second surface and a first conductivity type, forming a first GaN epitaxial layer of the first conductivity type coupled to the first surface of the substrate, and forming a second GaN epitaxial layer of a second conductivity type opposite to the first conductivity type. The second GaN epitaxial layer is coupled to the first GaN epitaxial layer. The method also includes implanting ions into a first region of the second GaN epitaxial layer to electrically isolate a second region of the second GaN epitaxial layer from a third region of the second GaN epitaxial layer. The method further includes forming an active device coupled to the second region of the second GaN epitaxial layer and forming the edge termination structure coupled to the third region of the second GaN epitaxial layer.

Abstract translation: 一种用于制造边缘终端结构的方法包括提供具有第一表面和第二表面和第一导电类型的衬底，形成耦合到衬底的第一表面的第一导电类型的第一GaN外延层，并形成第二 与第一导电类型相反的第二导电类型的GaN外延层。 第二GaN外延层耦合到第一GaN外延层。 该方法还包括将离子注入第二GaN外延层的第一区域以将第二GaN外延层的第二区域与第二GaN外延层的第三区域电隔离。 该方法还包括形成耦合到第二GaN外延层的第二区域并形成耦合到第二GaN外延层的第三区域的边缘端接结构的有源器件。

公开(公告)号：US20150263639A1

公开(公告)日：2015-09-17

申请号：US14213361

申请日：2014-03-14

Applicant: AVOGY, INC.

Inventor： Antoin Russell ,  Alberto Doronzo

IPC: H02M7/06 ,  H02M7/217

CPC classification number: H02M7/06 ,  H02M1/32 ,  H02M3/1588 ,  H02M3/33592 ,  H02M7/217 ,  H02M2001/0035 ,  H02M2001/0058 ,  H02M2001/0064 ,  Y02B70/1425 ,  Y02B70/1433 ,  Y02B70/1466 ,  Y02B70/1475 ,  Y02B70/1491 ,  Y02B70/16

Abstract: An embodiment of a resonant converter includes having resonant circuitry having inductive and capacitive elements configured to create electrical resonance when an input voltage is applied and a synchronous rectifier coupled between at least a portion of the resonant circuitry and an output of the resonant converter. The synchronous rectifier includes a diode, and an electrical switch. Control circuitry is configured to operate the electrical switch such that the electrical switch is turned on when there is substantially no voltage across the diode and current flow in the diode is positive in a direction from anode to cathode.

公开(公告)号：US20150255582A1

公开(公告)日：2015-09-10

申请号：US14657949

申请日：2015-03-13

Applicant: AVOGY, INC.

Inventor： Linda Romano ,  Andrew Edwards ,  Dave P. Bour ,  Isik C. Kizilyalli

IPC: H01L29/66 ,  H01L29/808

CPC classification number: H01L29/66916 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/452 ,  H01L29/66924 ,  H01L29/8083

Abstract: A vertical III-nitride field effect transistor includes a drain comprising a first III-nitride material, a drain contact electrically coupled to the drain, and a drift region comprising a second III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction. The field effect transistor also includes a channel region comprising a third III-nitride material coupled to the drift region, a gate region at least partially surrounding the channel region, and a gate contact electrically coupled to the gate region. The field effect transistor further includes a source coupled to the channel region. The source includes a GaN-layer coupled to an InGaN layer. The channel region is disposed between the drain and the source along the vertical direction such that current flow during operation of the vertical III-nitride field effect transistor is along the vertical direction.

Abstract translation: 垂直III族氮化物场效应晶体管包括：包含第一III族氮化物材料的漏极，与漏极电耦合的漏极接触点;以及漂移区域，包括耦合到漏极并邻近漏极设置的第二III族氮化物材料 垂直方向 场效应晶体管还包括沟道区，该沟道区包括耦合到漂移区的第三III族氮化物材料，至少部分围绕沟道区的栅极区和电耦合到栅极区的栅极接触。 场效应晶体管还包括耦合到沟道区的源极。 源包括耦合到InGaN层的GaN层。 沟道区域沿着垂直方向设置在漏极和源极之间，使得垂直III族氮化物场效应晶体管的工作期间的电流沿着垂直方向。

公开(公告)号：US20150179772A1

公开(公告)日：2015-06-25

申请号：US14489761

申请日：2014-09-18

Applicant: Avogy, Inc.

Inventor： Richard J. Brown ,  Isik C. Kizilyalli ,  Hui Nie ,  Andrew P. Edwards ,  David P. Bour

IPC: H01L29/66 ,  H01L21/32 ,  H01L29/47 ,  H01L21/02 ,  H01L29/20 ,  H01L29/36

CPC classification number: H01L29/66856 ,  H01L21/0254 ,  H01L21/02647 ,  H01L21/32 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/36 ,  H01L29/475 ,  H01L29/8083 ,  H01L29/812 ,  H01L29/8122

Abstract: A semiconductor structure includes a III-nitride substrate and a drift region coupled to the III-nitride substrate along a growth direction. The semiconductor substrate also includes a channel region coupled to the drift region. The channel region is defined by a channel sidewall disposed substantially along the growth direction. The semiconductor substrate further includes a gate region disposed laterally with respect to the channel region.

Abstract translation: 半导体结构包括III族氮化物衬底和沿生长方向耦合到III族氮化物衬底的漂移区域。 半导体衬底还包括耦合到漂移区的沟道区。 通道区域由基本沿着生长方向设置的通道侧壁限定。 半导体衬底还包括相对于沟道区域侧向设置的栅极区域。

公开(公告)号：US08941117B2

公开(公告)日：2015-01-27

申请号：US13935345

申请日：2013-07-03

Applicant: Avogy, Inc.

Inventor： Isik C. Kizilyalli ,  Hui Nie ,  Andrew P. Edwards ,  Linda Romano ,  David P. Bour ,  Richard J. Brown ,  Thomas R. Prunty

IPC: H01L31/0256 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109 ,  H01L29/66 ,  H01L29/808 ,  H01L29/872 ,  H01L29/20 ,  H01L27/06 ,  H01L27/07 ,  H01L27/098

CPC classification number: H01L29/66909 ,  H01L21/823487 ,  H01L27/0605 ,  H01L27/0611 ,  H01L27/0629 ,  H01L27/0727 ,  H01L27/098 ,  H01L29/2003 ,  H01L29/66143 ,  H01L29/8083 ,  H01L29/872

Abstract: An integrated device including a vertical III-nitride FET and a Schottky diode includes a drain comprising a first III-nitride material, a drift region comprising a second III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction, and a channel region comprising a third III-nitride material coupled to the drift region. The integrated device also includes a gate region at least partially surrounding the channel region, a source coupled to the channel region, and a Schottky contact coupled to the drift region. The channel region is disposed between the drain and the source along the vertical direction such that current flow during operation of the vertical III-nitride FET and the Schottky diode is along the vertical direction.

Abstract translation: 包括垂直III族氮化物FET和肖特基二极管的集成器件包括：包括第一III族氮化物材料的漏极，包括耦合到漏极并沿垂直方向邻近漏极设置的第二III族氮化物材料的漂移区， 以及包括耦合到所述漂移区的第三III族氮化物材料的沟道区。 集成器件还包括至少部分地围绕沟道区的栅极区域，耦合到沟道区的源极和耦合到漂移区域的肖特基接触。 沟道区域沿着垂直方向设置在漏极和源极之间，使得垂直III族氮化物FET和肖特基二极管的工作期间的电流沿垂直方向。

公开(公告)号：US20150017792A1

公开(公告)日：2015-01-15

申请号：US14498916

申请日：2014-09-26

Applicant: Avogy, Inc.

Inventor： David P. Bour ,  Richard J. Brown ,  Isik C. Kizilyalli ,  Thomas R. Prunty ,  Linda Romano ,  Andrew P. Edwards ,  Hui Nie ,  Mahdan Raj

IPC: H01L21/265 ,  H01L21/033 ,  H01L21/324 ,  H01L21/266

CPC classification number: H01L21/26546 ,  H01L21/0332 ,  H01L21/2258 ,  H01L21/266 ,  H01L21/3245 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/8083 ,  H01L29/861 ,  H01L29/872

Abstract: A method of forming a doped region in a III-nitride substrate includes providing the III-nitride substrate and forming a masking layer having a predetermined pattern and coupled to a portion of the III-nitride substrate. The III-nitride substrate is characterized by a first conductivity type and the predetermined pattern defines exposed regions of the III-nitride substrate. The method also includes heating the III-nitride substrate to a predetermined temperature and placing a dual-precursor gas adjacent the exposed regions of the III-nitride substrate. The dual-precursor gas includes a nitrogen source and a dopant source. The method further includes maintaining the predetermined temperature for a predetermined time period, forming p-type III-nitride regions adjacent the exposed regions of the III-nitride substrate, and removing the masking layer.

Abstract translation: 在III族氮化物衬底中形成掺杂区域的方法包括提供III族氮化物衬底并形成具有预定图案并与III族氮化物衬底的一部分耦合的掩模层。 III族氮化物衬底的特征在于第一导电类型，并且预定图案限定III族氮化物衬底的暴露区域。 该方法还包括将III族氮化物衬底加热到​​预定温度，并将双前体气体放置在III族氮化物衬底的暴露区域附近。 双前体气体包括氮源和掺杂剂源。 该方法还包括将预定温度保持预定时间段，形成与III族氮化物衬底的暴露区域相邻的p型III族氮化物区域，以及去除掩模层。