公开(公告)号：US20150008490A1

公开(公告)日：2015-01-08

申请号：US14024415

申请日：2013-09-11

Applicant: SEMI SOLUTIONS LLC ,  GOLD STANDARD SIMULATIONS LTD.

Inventor： Robert J. Strain ,  Asen Asenov

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/3083 ,  H01L29/1041 ,  H01L29/1054 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7853

Abstract: This improved, fluctuation resistant FinFET, with a doped core and lightly doped epitaxial channel region between that core and the gate structure, is confined to the active-gate span because it is based on a channel structure having a limited extent. The improved structure is capable of reducing FinFET random doping fluctuations when doping is used to control threshold voltage, and the channel structure reduces fluctuations attributable to doping-related variations in effective channel length. Further, the transistor design affords better source and drain conductance when compared to prior art FinFETs. Two representative embodiments of the key structure are described in detail.

Abstract translation: 这种改进的具有波动性的FinFET在该核心和栅极结构之间具有掺杂的核心和轻掺杂的外延沟道区域，被限制在有源栅极跨距，因为它基于具有有限程度的沟道结构。 当掺杂用于控制阈值电压时，改进的结构能够减少FinFET随机掺杂波动，并且沟道结构减少归因于有效沟道长度的掺杂相关变化的波动。 此外，与现有技术的FinFET相比，晶体管设计提供更好的源极和漏极电导。 详细描述密钥结构的两个代表性实施例。

公开(公告)号：US08207784B2

公开(公告)日：2012-06-26

申请号：US12370248

申请日：2009-02-12

Applicant: Yannis Tsividis

Inventor： Yannis Tsividis

IPC: H03K3/01

CPC classification number: G05F3/205 ,  H03K19/0013

Abstract: A method and apparatus is taught for reducing drain-source leakage in MOS circuits. In an exemplary CMOS inverter, a first transistor causes the body of an affected transistor to be at a first body potential. A second transistor brings the body potential of the affected transistor to a second body potential by providing an accurate body voltage from a body voltage source. Exemplary body bias voltage sources are further described that can drive one or more gate transistors of different gate circuits.

Abstract translation: 教导了用于减少MOS电路中的漏源泄漏的方法和装置。 在示例性的CMOS反相器中，第一晶体管使得受影响的晶体管的主体处于第一体电位。 第二晶体管通过从体电压源提供精确的体电压将受影响的晶体管的体电位带到第二体电位。 进一步描述可驱动不同门电路的一个或多个栅极晶体管的示例性体偏置电压源。

公开(公告)号：US07586155B2

公开(公告)日：2009-09-08

申请号：US11737559

申请日：2007-04-19

Applicant: Ashok Kumar Kapoor

Inventor： Ashok Kumar Kapoor

IPC: H01L23/62 ,  H01L27/088 ,  H03K17/16 ,  H03K3/01

CPC classification number: H03K19/0005 ,  H01L27/0629 ,  H01L2924/0002 ,  H03K19/0016 ,  H03K19/00361 ,  H01L2924/00

Abstract: An apparatus and method for manufacturing metal-oxide semiconductor (MOS) transistors that are operable at voltages below 1.5V, which MOS transistors are area efficient, and where the drive strength and leakage current of the MOS transistors is improved. The invention uses a dynamic threshold voltage control scheme that does not require a change to the existing MOS technology process. The invention provides a technique that controls the threshold voltage of the transistor. In the OFF state, the threshold voltage of the transistor is set high, keeping the transistor leakage to a small value. In the ON state, the threshold voltage is set to a low value, resulting in increased drive strength. The invention is particularly useful in MOS technology for both bulk and silicon on insulator (SOI) CMOS.

Abstract translation: 一种用于制造在低于1.5V的电压下操作的金属氧化物半导体（MOS）晶体管的装置和方法，其中MOS晶体管具有区域效率，并且其中提高了MOS晶体管的驱动强度和漏电流。 本发明使用不需要改变现有MOS技术过程的动态阈值电压控制方案。 本发明提供一种控制晶体管的阈值电压的技术。 在OFF状态下，将晶体管的阈值电压设定为高，将晶体管的漏电保持在较小的值。 在ON状态下，阈值电压设定为低值，导致驱动强度增加。 本发明在用于体积和绝缘体上硅（SOI）CMOS的MOS技术中特别有用。

公开(公告)号：US09379214B2

公开(公告)日：2016-06-28

申请号：US14616964

申请日：2015-02-09

Applicant: Semi Solutions LLC

Inventor： Ashok K. Kapoor ,  Robert J. Strain

IPC: H01L29/00 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/165

CPC classification number: H01L29/6659 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/324 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66492 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/7834

Abstract: A MOSFET structure and method of manufacture that minimize threshold variations associated with statistical uncertainties of implanted source and drain extensions. The source and drain extensions are fabricated very late in the process using a material added to etched recesses immediately adjacent to the transistor's channel. In various embodiments, the added material may be germanium grown by selective epitaxy, doped silicon grown by selective epitaxy, or metallic materials created by deposition or by deposition and reaction.

Abstract translation: 一种MOSFET结构和制造方法，其最小化与植入的源极和漏极扩展的统计学不确定性相关联的阈值变化。 源极和漏极延伸部分在工艺过程中使用添加到紧邻晶体管通道的蚀刻凹槽的材料制造得非常晚。 在各种实施例中，添加的材料可以是通过选择性外延生长的锗，通过选择性外延生长的掺杂硅，或通过沉积或沉积和反应产生的金属材料。

公开(公告)号：US20140103437A1

公开(公告)日：2014-04-17

申请号：US14051163

申请日：2013-10-10

Applicant: Gold Standard Simulations Ltd. ,  Semi Solutions LLC

Inventor： Ashok K. Kapoor ,  Robert J. Strain

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/66795 ,  H01L29/7853

Abstract: An improved fin field-effect transistor (FinFET) is built on a compound fin, which has a doped core and lightly doped epitaxial channel region between that core and the gate dielectric. The improved structure reduces FinFET random doping fluctuations when doping is used to control threshold voltage. Further, the transistor design affords better source and drain conductance when compared to prior art FinFETs. Three representative embodiments of the key structure are described in detail.

Abstract translation: 改进的鳍状场效应晶体管（FinFET）构建在复合鳍片上，复合鳍片在该芯体和栅极电介质之间具有掺杂的核心和轻掺杂的外延沟道区域。 当掺杂用于控制阈值电压时，改进的结构减少了FinFET随机掺杂波动。 此外，与现有技术的FinFET相比，晶体管设计提供更好的源极和漏极电导。 详细描述键结构的三个代表性实施例。

公开(公告)号：US08247840B2

公开(公告)日：2012-08-21

申请号：US12348797

申请日：2009-01-05

Applicant: Ashok Kumar Kapoor ,  Robert Strain

Inventor： Ashok Kumar Kapoor ,  Robert Strain

IPC: H01L29/66

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L27/0629 ,  H01L29/66636 ,  H01L29/7833 ,  H03K19/0005 ,  H03K19/0016 ,  H03K19/00361

Abstract: Use of a forward biased diode to reduce leakage current of transistors implemented on silicon on insulator (SOI) is a particular challenge due to the difficulty of achieving effective contact with the region beneath the gate of the transistor. An improved implementation in SOI gate fingers that reach under the source through tunnels that are contacted with a region outside the transistor. A further embodiment uses drain extension implants to provide good channel connection.

Abstract translation: 使用正向偏置二极管来减少在绝缘体上硅（SOI）上实现的晶体管的泄漏电流是一个特别的挑战，因为难以实现与晶体管栅极之下的区域的有效接触。 通过与晶体管外部的区域接触的隧道在源极下方的SOI栅极指中的改进的实现。 另一实施例使用漏极延伸植入物来提供良好的通道连接。

公开(公告)号：US07224205B2

公开(公告)日：2007-05-29

申请号：US11029542

申请日：2005-01-04

Applicant: Ashok Kumar Kapoor

Inventor： Ashok Kumar Kapoor

IPC: H03K3/01

CPC classification number: H03K19/0005 ,  H01L27/0629 ,  H01L2924/0002 ,  H03K19/0016 ,  H03K19/00361 ,  H01L2924/00

Abstract: An apparatus and method for manufacturing metal-oxide semiconductor (MOS) transistors that are operable at voltages below 1.5V, which MOS transistors are area efficient, and where the drive strength and leakage current of the MOS transistors is improved. The invention uses a dynamic threshold voltage control scheme that does not require a change to the existing MOS technology process. The invention provides a technique that controls the threshold voltage of the transistor. In the OFF state, the threshold voltage of the transistor is set high, keeping the transistor leakage to a small value. In the ON state, the threshold voltage is set to a low value, resulting in increased drive strength. The invention is particularly useful in MOS technology for both bulk and silicon on insulator (SOI) CMOS.

Abstract translation: 一种在低于1.5V的电压下工作的金属氧化物半导体（MOS）晶体管的装置和方法，其中MOS晶体管具有区域效率，并且其中MOS晶体管的驱动强度和漏电流得到改善。 本发明使用不需要改变现有MOS技术过程的动态阈值电压控制方案。 本发明提供一种控制晶体管的阈值电压的技术。 在OFF状态下，将晶体管的阈值电压设定为高，将晶体管的漏电保持在较小的值。 在ON状态下，阈值电压设定为低值，导致驱动强度增加。 本发明在用于体积和绝缘体上硅（SOI）CMOS的MOS技术中特别有用。

公开(公告)号：US07863689B2

公开(公告)日：2011-01-04

申请号：US12348809

申请日：2009-01-05

Applicant: Robert Strain

Inventor： Robert Strain

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L27/0629 ,  H01L27/0727 ,  H01L27/1203 ,  H01L29/47 ,  H01L29/78 ,  H01L29/872

Abstract: Deep submicron wells of MOS transistors, implemented over an ungrounded well, exhibit two modes of operation: a current sink mode and a current source mode. While operation as a current sink is well understood and successfully controlled, it is also necessary to control the current provided in the current source mode of the well. A Schottky diode is connected between the well and the gate, the Schottky diode having a smaller barrier height than that of the PN junction of the well-to-source. For an NMOS transistor, current flows through the PN junction when the gate is high. When the gate is low, current flows through the Schottky diode. This difference of current flow results in a difference in transistor threshold, thereby achieving a dynamic threshold voltage using the current from the well when operating at the current source mode.

Abstract translation: 在非接地井上实现的MOS晶体管的深亚微米阱具有两种工作模式：电流吸收模式和电流源模式。 当作为电流吸收器的操作被很好地理解并成功地控制时，还需要控制在井的当前源模式中提供的电流。 肖特基二极管连接在阱和栅极之间，肖特基二极管的栅极高度高于源阱的PN结的势垒高度。 对于NMOS晶体管，当栅极为高电平时，电流流过PN结。 当栅极低时，电流流过肖特基二极管。 电流的这种差异导致晶体管阈值的差异，从而当在当前源模式下工作时，使用来自阱的电流实现动态阈值电压。

公开(公告)号：US07691702B2

公开(公告)日：2010-04-06

申请号：US12109327

申请日：2008-04-24

Applicant: Ashok Kumar Kapoor

Inventor： Ashok Kumar Kapoor

IPC: H01L21/8239

CPC classification number: G11C11/4023 ,  G11C11/404 ,  G11C11/412 ,  G11C16/0416 ,  H01L27/1104

Abstract: In deep submicron memory arrays there is noted a relatively steady on current value and, therefore, threshold values of the transistors comprising the memory cell are reduced. This, in turn, results in an increase in the leakage current of the memory cell. With the use of an ever increasing number of memory cells leakage current must be controlled. A method of manufacture of a dynamic threshold voltage control scheme implemented with no more than minor changes to the existing MOS process technology is disclosed. The disclosed invention controls the threshold voltage of MOS transistors. Methods for enhancing the impact of the dynamic threshold control technology using this apparatus are also included. The invention is particularly useful for SRAM, DRAM, and NVM devices.

Abstract translation: 在深亚微米存储器阵列中，注意到电流值相对稳定，因此减小了包括存储器单元的晶体管的阈值。 这又导致存储单元的漏电流的增加。 随着使用越来越多的存储单元，必须控制漏电流。 公开了一种制造动态阈值电压控制方案，该方案仅对现有的MOS工艺技术进行了微小的改变。 所公开的发明控制MOS晶体管的阈值电压。 还包括用于增强使用该装置的动态阈值控制技术的影响的方法。 本发明对SRAM，DRAM和NVM器件特别有用。

公开(公告)号：US09847404B2

公开(公告)日：2017-12-19

申请号：US14024415

申请日：2013-09-11

Applicant: Gold Standard Simulations Ltd. ,  Semi Solutions LLC

Inventor： Robert J. Strain ,  Asen Asenov

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L21/308

CPC classification number: H01L29/66795 ,  H01L21/3083 ,  H01L29/1041 ,  H01L29/1054 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7853

Abstract: This improved, fluctuation resistant FinFET, with a doped core and lightly doped epitaxial channel region between that core and the gate structure, is confined to the active-gate span because it is based on a channel structure having a limited extent. The improved structure is capable of reducing FinFET random doping fluctuations when doping is used to control threshold voltage, and the channel structure reduces fluctuations attributable to doping-related variations in effective channel length. Further, the transistor design affords better source and drain conductance when compared to prior art FinFETs. Two representative embodiments of the key structure are described in detail.