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1.发明公开公开(公告)号：US20240312949A1
公开(公告)日：2024-09-19
申请号：US18306971
申请日：2023-04-25
发明人： Kang-Yun Yang , Yang-Tse Hung , Chao-Cheng Ku , Li-Yuan Lee
CPC分类号： H01L24/49 , G11C5/06 , G11C16/14 , H01L2224/4912
摘要： A layout structure of differential lines, a memory storage device and a memory control circuit unit are provided. The layout structure of the differential lines includes a wiring layer, a first wire and a second wire. The first wire is arranged on the wiring layer and configured to transmit a first differential signal. The second wire is arranged on the wiring layer and configured to transmit a second differential signal. A first end of the first wire and a first end of the second wire are coupled to a first electrical component. A second end of the first wire and a second end of the second wire are coupled to a second electrical component. The first end of the first wire has a first bending structure. One of the second end of the first wire and the second end of the second wire has a second bending structure.
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公开(公告)号：US20240304259A1
公开(公告)日：2024-09-12
申请号：US18298335
申请日：2023-04-10
发明人： Po-Cheng Su , Po-Hao Chen , Yu-Cheng Hsu , Wei Lin
CPC分类号： G11C16/26 , G11C16/08 , G11C16/3404
摘要： A voltage prediction method, a memory storage device and a memory control circuit unit are disclosed. The method includes: reading a plurality of memory cells in a rewritable non-volatile memory module by using a first read voltage level to obtain count information, and the first read voltage level is configured to distinguish a first state and a second state adjacent to each other in a threshold voltage distribution of the memory cells, and the count information reflects a total number of first memory cells meeting a target condition among the memory cells; and predicting a second read voltage level according to the count information, and the second read voltage level is configured to distinguish a third state and a fourth state adjacent to each other in the threshold voltage distribution.
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3.发明授权公开(公告)号：US12086419B2
公开(公告)日：2024-09-10
申请号：US17866569
申请日：2022-07-18
发明人： Chih-Kang Yeh
IPC分类号： G06F3/06
CPC分类号： G06F3/0616 , G06F3/0652 , G06F3/0679
摘要： A partial erasing management method, a memory storage device, and a memory control circuit unit are provided. The method includes: performing a first partial erasing operation on a first physical region among multiple physical regions in a first physical erasing unit to erase first data in the first physical region; after performing the first partial erasing operation on the first physical region, performing a first programming operation on the first physical region to store second data into the first physical region; and in response to at least one of the first partial erasing operation and the first programming operation, updating first status information related to the first physical region.
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公开(公告)号：US12008242B2
公开(公告)日：2024-06-11
申请号：US17983407
申请日：2022-11-09
发明人： Yi-Chung Chen , Ming-Chien Huang
IPC分类号： G06F3/06 , G11C11/4076
CPC分类号： G06F3/0614 , G06F3/0629 , G06F3/0673 , G11C11/4076
摘要： A signal calibration method, a memory storage device, and a memory control circuit unit are provided. The signal calibration method includes: generating a clock signal and a data strobe signal according to an internal clock signal; respectively transmitting the clock signal and the data strobe signal to a target volatile memory module among multiple volatile memory modules through a first signal path and a second signal path; obtaining a shift value between the data strobe signal and the clock signal at the target volatile memory module; and storing an initial delay setting of the data strobe signal according to delay information of the data strobe signal in response to the shift value being greater than a threshold value.
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公开(公告)号：US20240126313A1
公开(公告)日：2024-04-18
申请号：US18079900
申请日：2022-12-13
发明人： Po-Chih Ku
IPC分类号： G06F1/3234 , G06F1/3296
CPC分类号： G06F1/3275 , G06F1/3296
摘要： A regulator circuit module, a memory storage device, and a voltage control method are disclosed. The method includes: generating an output voltage according to an input voltage by a driving circuit; generating a feedback voltage according to the output voltage; controlling the driving circuit to adjust the output voltage according to the feedback voltage by a regulator circuit; compensating an output of the regulator circuit by a compensating circuit; and activating or deactivating the compensating circuit according to an input bypass-voltage of a switch circuit.
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公开(公告)号：US11809706B2
公开(公告)日：2023-11-07
申请号：US17349918
申请日：2021-06-17
发明人： Yu-Siang Yang , Yu-Cheng Hsu , Tsai-Hao Kuo , Wei Lin , An-Cheng Liu
IPC分类号： G06F3/06
CPC分类号： G06F3/0604 , G06F3/0619 , G06F3/0655 , G06F3/0679
摘要： A memory management method, a memory storage device, and a memory control circuit unit are provided. The method includes: reading first data from a first physical unit by using a first read voltage level according to first management information among multiple candidate management information; decoding the first data and recording first error bit information of the first data; and adjusting sorting information related to the candidate management information according to the first error bit information. The sorting information reflects a usage order of the candidate management information in a decoding operation.
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7.发明公开公开(公告)号：US20230297464A1
公开(公告)日：2023-09-21
申请号：US17715050
申请日：2022-04-07
发明人： Kok-Yong Tan
CPC分类号： G06F11/0793 , G06F1/30 , G06F11/073 , G06F3/0625 , G06F3/065 , G06F3/0689 , G06F3/0619
摘要： An abnormal power loss recovery method, a memory control circuit unit, and a memory storage device are provided. The method is configured for a memory storage device including a rewritable non-volatile memory module having a plurality of super-physical units. The super-physical units include at least two physical erasing units, and each of the physical erasing units belongs to a different operation unit and includes a plurality of physical programming units. The method includes: reading data stored in a first super-physical unit without a corresponding RAID ECC code when a memory storage device is powered on again and detected as an abnormal power loss to obtain first data, and the first super-physical unit is a last super-physical unit to which data is written before the abnormal power loss occurs; and copying the first data to a second super-physical unit.
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公开(公告)号：US20230297233A1
公开(公告)日：2023-09-21
申请号：US17721358
申请日：2022-04-15
发明人： Chih-Kang Yeh
IPC分类号： G06F3/06
CPC分类号： G06F3/0604 , G06F3/0652 , G06F3/0679
摘要： A memory management method configured for a rewritable non-volatile memory module, a memory storage device, and a memory control circuit unit are provided. The rewritable non-volatile memory module includes a plurality of dies, wherein each of the dies includes a plurality of planes, each of the planes includes a plurality of physical erasing units, and a sum of a number of the planes included in the rewritable non-volatile memory module is a first number. The method includes: grouping the plurality of physical erasing units into a plurality of management units. Each of the plurality of physical erasing units included in each of the management units belongs to a different plane, and each of the management units has a second number of the physical erasing units, wherein the second number is less than the first number.
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公开(公告)号：US20230289102A1
公开(公告)日：2023-09-14
申请号：US17724504
申请日：2022-04-20
发明人： Yu-Hsiang Lin , Bo Lun Huang
IPC分类号： G06F3/06
CPC分类号： G06F3/0659 , G06F3/0604 , G06F3/0679
摘要： An encoding control method, a memory storage device and a memory control circuit unit are disclosed. The method includes: performing, by an encoding circuit, a first encoding operation to generate first parity data according to write data, a first sub-matrix and a second sub-matrix of a parity check matrix; performing, by the encoding circuit, a second encoding operation to generate second parity data according to the write data, the first parity data, a third sub-matrix, a fourth sub-matrix and a fifth sub-matrix of the parity check matrix; and sending a first write command sequence to instruct a storing of the write data, the first parity data and the second parity data to a rewritable non-volatile memory module.
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公开(公告)号：US11757684B2
公开(公告)日：2023-09-12
申请号：US17543741
申请日：2021-12-07
发明人： Chun-Wei Chang , Ching-Jui Hsiao , Jen-Chu Wu , Yuwei Kuo
IPC分类号： H04L25/49
CPC分类号： H04L25/4904
摘要： A retiming circuit module, a signal transmission system, and a signal transmission method are provided. The retiming circuit module includes a path control circuit and a multipath signal transmission circuit. The multipath signal transmission circuit includes built-in first signal transmission path and second signal transmission path. The multipath signal transmission circuit may perform first signal transmission between an upstream device and a downstream device based on a first signal transmission frequency and the second signal transmission path. During a period of performing the first signal transmission, the path control circuit may detect a first data sequence transmitted between the upstream device and the downstream device. The path control circuit may control the multipath signal transmission circuit to switch to perform second signal transmission between the upstream device and the downstream device based on the first signal transmission frequency and the first signal transmission path according to the first data sequence.
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