公开(公告)号：US20140145259A1

公开(公告)日：2014-05-29

申请号：US14169627

申请日：2014-01-31

申请人： HITACHI ULSI SYSTEMS CO., LTD. ,  RENESAS ELECTRONICS CORPORATION

发明人： Hiroshi INAGAWA ,  Nobuo MACHIDA ,  Kentaro OOISHI

IPC分类号： H01L29/78 ,  H01L27/088

CPC分类号： H01L29/66734 ,  H01L21/02532 ,  H01L21/266 ,  H01L21/76897 ,  H01L27/0255 ,  H01L27/0629 ,  H01L27/088 ,  H01L29/0611 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/4232 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66727 ,  H01L29/7804 ,  H01L29/7808 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827

摘要： A semiconductor device has an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. The conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. After etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate, a channel region and a source region are formed by ion implantation so that the semiconductor device is free from occurrence of a source offset.

摘要翻译： 半导体器件具有沟槽栅极结构的FET，其通过在半导体衬底的主表面中延伸的沟槽中设置作为栅极的导电层而获得，其中沟槽栅极导电层的上表面是 形成为等于或高于半导体衬底的主表面。 沟槽栅极的导电层形成为具有基本平坦或凹入的上表面，并且上表面形成为等于或高于半导体衬底的主表面。 在蚀刻半导体衬底以形成沟槽栅极的导电层的上表面之后，通过离子注入形成沟道区域和源极区域，使得半导体器件不发生源极偏移。

公开(公告)号：US20130145084A1

公开(公告)日：2013-06-06

申请号：US13692506

申请日：2012-12-03

申请人： Hitachi ULSI Systems Co., Ltd.

发明人： Ayumi HIROMATSU ,  Masahiro KATAYAMA ,  Takanaga YAMAZAKI

IPC分类号： G06F12/02 ,  H04L7/033

CPC分类号： G06F12/0246 ,  H04L7/033 ,  H04L7/0331 ,  H04L25/0262 ,  H04L25/38

摘要： An electronic apparatus provided with a serial communication circuit achieving a baud rate adjustment with high precision is provided. For example, a bit width of each of a plurality of bits in received serial data is measured by a clock counter, and an average value of the bit width is calculated detecting its maximum value and minimum value. Moreover, for example, a maximum tolerance and a minimum tolerance are calculated as a value substantially 1.5 times the average value and a value substantially 0.5 times the average value, and determination is made as to whether or not the maximum value and the minimum value are within a range between the maximum tolerance and the minimum tolerance. If they are within the range, the corresponding average value is set in a baud rate setting register.

摘要翻译： 提供了具有实现高精度的波特率调整的串行通信电路的电子设备。 例如，通过时钟计数器测量接收到的串行数据中的多个比特的比特宽度，并且计算其宽度的平均值来检测其最大值和最小值。 此外，例如，最大公差和最小公差被计算为基本上为平均值的1.5倍的值和基本上为平均值的0.5倍的值，并且确定最大值和最小值是否为 在最大公差和最小公差之间的范围内。 如果它们在范围内，则在波特率设置寄存器中设置相应的平均值。

公开(公告)号：US20130024673A1

公开(公告)日：2013-01-24

申请号：US13555126

申请日：2012-07-21

申请人： Takanaga YAMAZAKI

发明人： Takanaga YAMAZAKI

IPC分类号： G06F9/30

CPC分类号： G06F9/30072 ,  G06F9/3001 ,  G06F9/30032 ,  G06F9/30079

摘要： A technology capable of reducing load on both system processing and filter operation and improving power consumption and performance is provided. In a digital signal processor, a program memory, a program counter, and a control logic circuit are provided, and a bit field of each instruction includes instruction stop flag information and bit field information. Also, the control logic circuit carries out the control in such a manner that the instruction whose instruction stop flag information is cleared is executed as is to proceed to the next instruction processing, execution of the instruction whose instruction stop flag information is set is stopped if an execution resumption trigger condition corresponding to the bit field information is not satisfied, and the instruction whose instruction stop flag information is set is executed if the execution resumption trigger condition corresponding to bit field information is satisfied, to proceed to the next instruction processing.

摘要翻译： 提供了一种能够减少系统处理和滤波操作负载并提高功耗和性能的技术。 在数字信号处理器中，提供程序存储器，程序计数器和控制逻辑电路，并且每个指令的位字段包括指令停止标志信息和位字段信息。 此外，控制逻辑电路执行控制，使得指令停止标志信息被清除的指令被执行，以进行下一个指令处理，停止指令停止标志信息的指令的执行如果 与位字段信息相对应的执行恢复触发条件不满足，并且如果满足与位字段信息对应的执行恢复触发条件，则执行指令停止标志信息被设置的指令，以进行下一个指令处理。

公开(公告)号：US20120294081A1

公开(公告)日：2012-11-22

申请号：US13479240

申请日：2012-05-23

申请人： HIROYUKI MIZUNO ,  TAKESHI SAKATA ,  NOBUHIRO OODAIRA ,  TAKAO WATANABE ,  YUSUKE KANNO

发明人： HIROYUKI MIZUNO ,  TAKESHI SAKATA ,  NOBUHIRO OODAIRA ,  TAKAO WATANABE ,  YUSUKE KANNO

IPC分类号： G11C11/40

CPC分类号： G11C11/4076 ,  G11C7/04 ,  G11C7/065 ,  G11C7/08 ,  G11C7/12 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  G11C2207/002 ,  G11C2207/005

摘要： In a sense circuit for DRAM memory cell a switch is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines. The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. VDL is the maximum amplitude voltage of the bit line BL. A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data. When the bit line BL and local bit line LBL are capacitance-coupled via a capacitor, it is recommended to use a latch type sense amplifier SA connected to the local bit line LBL.

摘要翻译： 在用于DRAM存储单元的感测电路中，在位线BL和连接到存储器单元的局部位线LBL之间提供开关以隔离和耦合这些位线。 位线BL被预充电到VDL / 2的电压，而局部位线LBL被预充电到VDL的电压。 VDL是位线BL的最大幅度电压。 读出放大器SA包括第一电路，其包括具有连接到位线BL的栅极的差分MOS对，以及连接到用于全幅放大的局部位线LBL并用于保持该数据的第二电路。 当位线BL和本地位线LBL通过电容器电容耦合时，建议使用连接到局部位线LBL的锁存型读出放大器SA。

公开(公告)号：US08293648B2

公开(公告)日：2012-10-23

申请号：US13239571

申请日：2011-09-22

申请人： Takuya Futase ,  Tomonori Saeki ,  Mieko Kashi

发明人： Takuya Futase ,  Tomonori Saeki ,  Mieko Kashi

IPC分类号： H01L21/44

CPC分类号： C23F1/30 ,  H01L21/32134 ,  H01L27/10814 ,  H01L28/55 ,  H01L28/60 ,  Y10S134/902

摘要： In order to prevent the contamination of wafers made of a transition metal in a semiconductor mass production process, the mass production method of a semiconductor integrated circuit device of the invention comprises the steps of depositing an Ru film on individual wafers passing through a wafer process, removing the Ru film from outer edge portions of a device side and a back side of individual wafers, on which said Ru film has been deposited, by means of an aqueous solution containing orthoperiodic acid and nitric acid, and subjecting said individual wafers, from which said Ru film has been removed, to a lithographic step, an inspection step or a thermal treating step that is in common use relation with a plurality of wafers belonging to lower layer steps (an initial element formation step and a wiring step prior to the formation of a gate insulating film).

摘要翻译： 为了防止在半导体批量生产工艺中由过渡金属制成的晶片的污染，本发明的半导体集成电路器件的批量生产方法包括以下步骤：在通过晶片工艺的各个晶片上沉积Ru膜， 通过含有正周期酸和硝酸的水溶液从沉积有Ru膜的单个晶片的器件侧和背面的外边缘部分去除Ru膜，并对其进行处理 所述Ru膜已被去除，涉及光刻步骤，与属于下层步骤的多个晶片（初始元素形成步骤和形成前的布线步骤）具有通用关系的检查步骤或热处理步骤 的栅极绝缘膜）。

公开(公告)号：US20120154965A1

公开(公告)日：2012-06-21

申请号：US13406715

申请日：2012-02-28

申请人： Kazuo Tanaka ,  Hiroyuki Mizuno ,  Rie Nishiyama ,  Manabu Miyamoto

发明人： Kazuo Tanaka ,  Hiroyuki Mizuno ,  Rie Nishiyama ,  Manabu Miyamoto

IPC分类号： H02H9/04

CPC分类号： H03K3/356113 ,  H01L2924/0002 ,  H03K3/356104 ,  H01L2924/00

摘要： In a level conversion circuit mounted in an integrated circuit device using a plurality of high- and low-voltage power supplies, the input to the differential inputs are provided. In a level-down circuit, MOS transistors that are not supplied with 3.3 V between the gate and drain and between the gate and source use a thin oxide layer. In a level-up circuit, a logic operation function is provided.

摘要翻译： 在安装在使用多个高压和低压电源的集成电路装置中的电平转换电路中，提供到差分输入的输入。 在降压电路中，栅极和漏极之间以及栅极和源极之间未提供3.3 V的MOS晶体管使用薄的氧化物层。 在升高电路中，提供逻辑运算功能。

公开(公告)号：US20120052675A1

公开(公告)日：2012-03-01

申请号：US13291999

申请日：2011-11-08

申请人： Sumito Numazawa ,  Yoshito Nakazawa ,  Masayoshi Kobayashi ,  Satoshi Kudo ,  Yasuo Imai ,  Sakae Kubo ,  Takashi Shigematsu ,  Akihiro Ohnishi ,  Kozo Uesawa ,  Kentaro Oishi

发明人： Sumito Numazawa ,  Yoshito Nakazawa ,  Masayoshi Kobayashi ,  Satoshi Kudo ,  Yasuo Imai ,  Sakae Kubo ,  Takashi Shigematsu ,  Akihiro Ohnishi ,  Kozo Uesawa ,  Kentaro Oishi

IPC分类号： H01L21/28

CPC分类号： H01L21/28114 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L29/0696 ,  H01L29/0869 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/511 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827

摘要： In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.

摘要翻译： 在制造具有沟槽栅极结构的MISFET的半导体器件的方法中，从半导体层的方向的深度方向上的第一导电类型的半导体层的主表面形成沟槽， 在沟槽的内表面上形成包括热氧化膜和沉积膜的栅极绝缘膜，并且在沟槽中形成栅电极之后，将杂质引入到第一导电类型的半导体衬底中以形成 用作沟道形成区域的第二导电类型的半导体区域，并且将杂质引入到第二导电类型的半导体区域中，以形成用作源极区域的第一导电类型的半导体区域。

公开(公告)号：US20120009800A1

公开(公告)日：2012-01-12

申请号：US13239571

申请日：2011-09-22

申请人： Takuya FUTASE ,  Tomonori Saeki ,  Mieko Kashi

发明人： Takuya FUTASE ,  Tomonori Saeki ,  Mieko Kashi

IPC分类号： H01L21/02

CPC分类号： C23F1/30 ,  H01L21/32134 ,  H01L27/10814 ,  H01L28/55 ,  H01L28/60 ,  Y10S134/902

摘要： In order to prevent the contamination of wafers made of a transition metal in a semiconductor mass production process, the mass production method of a semiconductor integrated circuit device of the invention comprises the steps of depositing an Ru film on individual wafers passing through a wafer process, removing the Ru film from outer edge portions of a device side and a back side of individual wafers, on which said Ru film has been deposited, by means of an aqueous solution containing orthoperiodic acid and nitric acid, and subjecting said individual wafers, from which said Ru film has been removed, to a lithographic step, an inspection step or a thermal treating step that is in common use relation with a plurality of wafers belonging to lower layer steps (an initial element formation step and a wiring step prior to the formation of a gate insulating film).

摘要翻译： 为了防止在半导体批量生产工艺中由过渡金属制成的晶片的污染，本发明的半导体集成电路器件的批量生产方法包括以下步骤：在通过晶片工艺的各个晶片上沉积Ru膜， 通过含有正周期酸和硝酸的水溶液从沉积有Ru膜的单个晶片的器件侧和背面的外边缘部分去除Ru膜，并对其进行处理 所述Ru膜已被去除，涉及光刻步骤，与属于下层步骤的多个晶片（初始元素形成步骤和形成前的布线步骤）具有通用关系的检查步骤或热处理步骤 的栅极绝缘膜）。

公开(公告)号：US08042021B2

公开(公告)日：2011-10-18

申请号：US13089310

申请日：2011-04-18

申请人： Takayuki Tamura ,  Hirofumi Shibuya ,  Hiroyuki Goto ,  Shigemasa Shiota

发明人： Takayuki Tamura ,  Hirofumi Shibuya ,  Hiroyuki Goto ,  Shigemasa Shiota

IPC分类号： G11C29/00 ,  G11C16/04 ,  G06F12/00

CPC分类号： G11C29/76 ,  G06F11/1068 ,  G06F13/1673 ,  G11C5/04 ,  G11C29/72 ,  G11C2029/0409

摘要： A memory card has a plurality of non-volatile memories and a main controller for controlling the operation of the non-volatile memories. The main controller performs an access control to the non-volatile memories in response to an external access instruction, and an alternate control for alternating an access error-related storage area of the non-volatile memory with other storage area. In the access control, the speeding up of the data transfer between flash memories is achieved by causing the plurality of non-volatile memories to parallel access operate. In the alternation control, the storage areas is made alternative for each non-volatile memory in which an access error occurs.

摘要翻译： 存储卡具有多个非易失性存储器和用于控制非易失性存储器的操作的主控制器。 主控制器响应于外部访问指令对非易失性存储器执行访问控制，以及用于将非易失性存储器的访问错误相关存储区域与其他存储区域交替的替代控制。 在访问控制中，通过使多个非易失性存储器并行访问操作来实现闪速存储器之间的数据传输的加速。 在交替控制中，对于发生访问错误的每个非易失性存储器，存储区域被替代。

公开(公告)号：US08018006B2

公开(公告)日：2011-09-13

申请号：US12759188

申请日：2010-04-13

申请人： Mitsuru Arai ,  Shinichiro Wada ,  Hideaki Nonami

发明人： Mitsuru Arai ,  Shinichiro Wada ,  Hideaki Nonami

IPC分类号： H01L21/70

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/0692 ,  H01L29/7317 ,  H01L29/732

摘要： A semiconductor device includes a lower substrate, a thin semiconductor layer and an insulating layer formed between the lower substrate and the semiconductor layer. An active transistor area is formed with a base formed along a surface of the semiconductor layer, an emitter region formed in the base, a buried collector in the thin semiconductor layer to contact the insulating layer, a collector contacting the buried collector, and emitter, collector and base contacts. The active transistor area is configured to operate at an emitter current at least in the order of mA (milli-ampere). An isolation trench extends through the semiconductor layer to the insulating layer and surrounds the active transistor area with a distance in the order of μm (micron) from the active transistor area and with a space area of more than 50 μm2 between the active transistor area and the isolation trench.

摘要翻译： 半导体器件包括下基板，薄半导体层和形成在下基板和半导体层之间的绝缘层。 有源晶体管区域形成有沿着半导体层的表面形成的基底，形成在基底中的发射极区域，薄的半导体层中的与绝缘层接触的掩埋集电极，与埋入集电极接触的集电极和发射极， 收集器和基座触点。 有源晶体管区域被配置为以至少大约数毫安（毫安）的发射极电流工作。 隔离沟槽延伸穿过半导体层到绝缘层并且围绕有源晶体管区域，距离有源晶体管区域的距离为μm（微米），并且在有源晶体管区域与有源晶体管区域之间具有大于50μm2的空间区域 隔离沟。