公开(公告)号：US08044488B2

公开(公告)日：2011-10-25

申请号：US12144042

申请日：2008-06-23

申请人： Mitsuru Arai ,  Shinichiro Wada ,  Hideyuki Hosoe

发明人： Mitsuru Arai ,  Shinichiro Wada ,  Hideyuki Hosoe

IPC分类号： H01L21/70

CPC分类号： H01L29/732 ,  H01L21/8222 ,  H01L27/0825 ,  H01L27/1203 ,  H01L29/7317

摘要： The invention is based upon a semiconductor device where a high voltage bipolar transistor is manufactured on the same wafer with a high-speed bipolar transistor, and has a characteristic that the high-speed bipolar transistor and the high voltage bipolar transistor are formed on each epitaxial collector layer having the same thickness and are provided with a buried collector region formed in the same process and having the same impurity profile, the buried collector region exists immediately under a base of the high-speed bipolar transistor, no buried collector region and no SIC region exist immediately under a base of the high voltage bipolar transistor and distance between a base region and a collector plug region of the high voltage bipolar transistor is equal to or is longer than the similar distance of the high-speed bipolar transistor.

摘要翻译： 本发明基于一种半导体器件，其中在具有高速双极晶体管的相同晶片上制造高电压双极晶体管，并且具有在每个外延上形成高速双极晶体管和高压双极晶体管的特性 具有相同厚度的集电极层，并且具有形成在相同工艺中并且具有相同杂质分布的掩埋集电极区域，所述掩埋集电极区域直接存在于高速双极晶体管的基极的下方，没有掩埋集电极区域而没有SIC 区域立即存在于高电压双极晶体管的基极之下，并且高电压双极晶体管的基极区域和集电极插塞区域之间的距离等于或长于高速双极晶体管的类似距离。

公开(公告)号：US5565907A

公开(公告)日：1996-10-15

申请号：US230558

申请日：1994-04-20

申请人： Shinichiro Wada ,  Takahiro Yagishita

发明人： Shinichiro Wada ,  Takahiro Yagishita

IPC分类号： G06K15/12 ,  H04N1/405 ,  H04N1/21

CPC分类号： H04N1/4058 ,  G06K15/1223

摘要： An image forming apparatus capable of producing a high quality halftone image stably and rendering faithful tonality. For a bilevel image, the apparatus smooths the boundary between black and white. For a multilevel image, the apparatus obviates solitary dots for thereby causing dots to concentrate. As a result, a bilevel image and a multilevel image are provided with a clear boundary.

摘要翻译： 一种图像形成装置，能够稳定地产生高质量的半色调图像并且实现忠实的色调。 对于双色图像，设备使黑色和白色之间的边界平滑。 对于多级图像，该装置避免了孤立点，从而导致点集中。 结果，双层图像和多层图像具有清晰的边界。

公开(公告)号：US5194879A

公开(公告)日：1993-03-16

申请号：US658780

申请日：1991-02-21

申请人： Hiroaki Kotabe ,  Shigeru Yamazaki ,  Kouji Yamanobe ,  Masaru Kaneko ,  Yasushi Nakazato ,  Masahiko Banno ,  Shinichiro Wada ,  Akihiko Motegi ,  Kazuya Iwasaki ,  Takashi Nishizawa

发明人： Hiroaki Kotabe ,  Shigeru Yamazaki ,  Kouji Yamanobe ,  Masaru Kaneko ,  Yasushi Nakazato ,  Masahiko Banno ,  Shinichiro Wada ,  Akihiko Motegi ,  Kazuya Iwasaki ,  Takashi Nishizawa

IPC分类号： B41J2/44 ,  G02B26/10 ,  G03G15/04 ,  G06K15/12 ,  H04N1/113 ,  H04N1/17 ,  H04N1/405

CPC分类号： H04N1/4056 ,  G06K15/1204

摘要： An image forming apparatus includes a laser beam scanning unit for scanning a recording medium in synchronism with a writing clock signal so that a dotted image is formed on the recording medium, a counter for carrying out a count operation in synchronism with the writing clock signal so that one count value or a plurality of count values determining a scanning area is/are obtained, a first controller for activating or inactivating the laser beam scanning unit based on one or the plurality of count values, a dip switch unit for specifying a dotting density, a second controller for controlling the frequency of the writing clock signal and/or a speed of scanning; and a changing unit for changing one or the plurality of count values, which should be obtained by the counter, based on the dotting density specified by the dip switch unit, so that the position of the scanning area with respect to the recording medium is constant even if the frequency of the writing clock signal and/or the scanning speed are changed by the second controller.

摘要翻译： 图像形成装置包括：激光束扫描单元，用于与写入时钟信号同步地扫描记录介质，使得在记录介质上形成点状图像;计数器，用于与写时钟信号同步地执行计数操作; 确定确定扫描区域的一个计数值或多个计数值，用于基于一个或多个计数值激活或者激活激光束扫描单元的第一控制器，用于指定点密度的dip开关单元 ，用于控制写入时钟信号的频率和/或扫描速度的第二控制器; 以及改变单元，用于基于由dip开关单元指定的点数密度来改变由计数器获得的一个或多个计数值，使得扫描区域相对于记录介质的位置是恒定的 即使第二控制器改变写入时钟信号的频率和/或扫描速度。

公开(公告)号：US08546213B2

公开(公告)日：2013-10-01

申请号：US12962631

申请日：2010-12-07

申请人： Tomoyuki Miyoshi ,  Shinichiro Wada ,  Yohei Yanagida

发明人： Tomoyuki Miyoshi ,  Shinichiro Wada ,  Yohei Yanagida

IPC分类号： H01L21/8234

CPC分类号： H01L29/8611 ,  H01L27/0255 ,  H01L27/0629 ,  H01L29/0692 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/66128 ,  H01L29/66136 ,  H01L29/66681 ,  H01L29/7816

摘要： A high voltage ESD protective diode having high avalanche withstand capability and capable of being formed by using manufacturing steps identical with those for a high voltage transistor to be protected, the device having a structure in which a gate oxide film is formed over a substrate surface at a PN junction formed of an N type low concentration semiconductor substrate constituting a cathode region and a P type low concentration diffusion region constituting an anode region, and a gate electrode which is disposed overriding the gate oxide film and a field oxide film is connected electrically by way of a gate plug with an anode electrode, whereby an electric field at the PN junction is moderated upon avalanche breakdown to obtain a high avalanche withstand capability. Further, the withstand voltage can be adjusted by changing the length of the field oxide film.

摘要翻译： 一种具有高雪崩性能的高电压ESD保护二极管，其能够通过使用与待保护的高电压晶体管相同的制造步骤而形成，该器件具有其中栅极氧化膜形成在衬底表面上的结构 由构成阴极区域的N型低浓度半导体衬底和构成阳极区域的P型低浓度扩散区域形成的PN结以及覆盖栅极氧化膜和场氧化膜的栅电极通过 具有阳极电极的栅极插塞的方式，由此在雪崩击穿时PN结处的电场缓和以获得高雪崩承受能力。 此外，可以通过改变场氧化物膜的长度来调节耐受电压。

公开(公告)号：US08368151B2

公开(公告)日：2013-02-05

申请号：US12644461

申请日：2009-12-22

申请人： Kenji Miyakoshi ,  Shinichiro Wada ,  Junji Noguchi ,  Koichiro Miyamoto ,  Masaya Iida ,  Masafumi Suefuji

发明人： Kenji Miyakoshi ,  Shinichiro Wada ,  Junji Noguchi ,  Koichiro Miyamoto ,  Masaya Iida ,  Masafumi Suefuji

IPC分类号： H01L21/8234 ,  H01L27/088

CPC分类号： H01L21/823412

摘要： When MOS transistors having a plurality of threshold voltages in which a source and a drain form a symmetrical structure are mounted on the same substrate, electrically-symmetrical characteristics is provided with respect to an exchange of the source and the drain in each MOS transistor. A MOS transistor having a large threshold voltage is provided with a halo diffusion region, and halo implantation is not performed on a MOS transistor having a small threshold voltage.

摘要翻译： 当源极和漏极形成对称结构的多个阈值电压的MOS晶体管被安装在同一衬底上时，相对于每个MOS晶体管中的源极和漏极的交换来提供电对称特性。 具有大阈值电压的MOS晶体管具有卤素扩散区域，并且不对具有小阈值电压的MOS晶体管进行晕圈注入。

公开(公告)号：US20110140199A1

公开(公告)日：2011-06-16

申请号：US12962631

申请日：2010-12-07

申请人： Tomoyuki MIYOSHI ,  Shinichiro Wada ,  Yohei Yanagida

发明人： Tomoyuki MIYOSHI ,  Shinichiro Wada ,  Yohei Yanagida

IPC分类号： H01L27/07 ,  H01L21/8234

CPC分类号： H01L29/8611 ,  H01L27/0255 ,  H01L27/0629 ,  H01L29/0692 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/66128 ,  H01L29/66136 ,  H01L29/66681 ,  H01L29/7816

摘要： A high voltage ESD protective diode having high avalanche withstand capability and capable of being formed by using manufacturing steps identical with those for a high voltage transistor to be protected, the device having a structure in which a gate oxide film is formed over a substrate surface at a PN junction formed of an N type low concentration semiconductor substrate constituting a cathode region and a P type low concentration diffusion region constituting an anode region, and a gate electrode which is disposed overriding the gate oxide film and a field oxide film is connected electrically by way of a gate plug with an anode electrode, whereby an electric field at the PN junction is moderated upon avalanche breakdown to obtain a high avalanche withstand capability. Further, the withstand voltage can be adjusted by changing the length of the field oxide film.

摘要翻译： 一种具有高雪崩性能的高电压ESD保护二极管，其能够通过使用与待保护的高电压晶体管相同的制造步骤而形成，该器件具有其中栅极氧化膜形成在衬底表面上的结构 由构成阴极区域的N型低浓度半导体衬底和构成阳极区域的P型低浓度扩散区域形成的PN结以及覆盖栅极氧化膜和场氧化膜的栅电极通过 具有阳极电极的栅极插塞的方式，由此在雪崩击穿时PN结处的电场缓和以获得高雪崩承受能力。 此外，可以通过改变场氧化物膜的长度来调节耐受电压。

公开(公告)号：US06924544B2

公开(公告)日：2005-08-02

申请号：US10766182

申请日：2004-01-29

申请人： Shinichiro Wada ,  Hiromi Shimamoto

发明人： Shinichiro Wada ,  Hiromi Shimamoto

IPC分类号： H01L21/331 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8222 ,  H01L21/8234 ,  H01L27/04 ,  H01L27/06 ,  H01L27/08 ,  H01L29/732 ,  H01L29/737 ,  H01L29/00

CPC分类号： H01L28/20 ,  H01L27/0629 ,  H01L27/0802

摘要： A semiconductor device with a resistor element whose the resistance value can be adjusted to a desired value without changing dimensions thereof is provided. The resistor element is formed of a poly-Si layer formed on an insulator over a semiconductor substrate. An impurity is introduced into the poly-Si layer by the use of ion implantation. In the vicinity of both ends of the poly-Si layer forming the resistor element, silicide layers each made of cobalt silicide or the like are formed over an upper surface of the poly-Si layer. The area of one silicide layer is larger than that of the other silicide layer. By adjusting the area of the one silicide layer, the length between the silicide layers is adjusted and the resistance value of the resistor element can be adjusted without changing the shape of the poly-Si layer.

摘要翻译： 提供一种具有电阻元件的半导体器件，其电阻值可以被调节到期望值而不改变其尺寸。 电阻元件由在半导体衬底上的绝缘体上形成的多晶硅层形成。 通过使用离子注入将杂质引入多晶硅层。 在形成电阻元件的多晶硅层的两端附近，在多晶硅层的上表面上形成由硅化钴等构成的硅化物层。 一个硅化物层的面积大于另一个硅化物层的面积。 通过调整一个硅化物层的面积，调整硅化物层之间的长度，并且可以在不改变多晶硅层的形状的情况下调节电阻元件的电阻值。

公开(公告)号：US20050040869A1

公开(公告)日：2005-02-24

申请号：US10948304

申请日：2004-09-24

申请人： Shinichiro Wada ,  Satoshi Ueno ,  Shinya Kajiyama

发明人： Shinichiro Wada ,  Satoshi Ueno ,  Shinya Kajiyama

IPC分类号： H01L27/06 ,  H01L21/8249 ,  H03K19/08 ,  H03M9/00 ,  H03B19/00

CPC分类号： H03M9/00

摘要： In a circuit for converting an input signal Data1 of high frequency to an output signal Data4 of low frequency, a signal of the frequency band (for example, 10 GHz to 2.5 GHz) which can be processed only with a bipolar ECL circuit is processed with a bipolar ECL circuit. After the frequency of signal up to the maximum frequency which can be processed with a CMOS circuit is lowered, the signal is inputted to the CMOS circuit via a level conversion circuit in order to lower the frequency (for example, 2.5 GHz to 1.25 GHz). Thereby, power consumption of the semiconductor integrated circuit device, particularly the device including the Bi-CMOS circuit can be lowered while high-seed processing characteristic in the signal process of the circuit is maintained.

摘要翻译： 在用于将高频输入信号Data1转换为低频输出信号Data4的电路中，仅用双极性ECL电路处理的频带（例如，10GHz至2.5GHz）的信号被处理 双极ECL电路。 在可以用CMOS电路处理的信号的频率达到最大频率之后，信号通过电平转换电路输入到CMOS电路，以便降低频率（例如，2.5GHz至1.25GHz） 。 由此，可以降低半导体集成电路器件的功耗，特别是包括Bi-CMOS电路的器件，同时保持电路的信号处理中的高种子处理特性。

公开(公告)号：US5892595A

公开(公告)日：1999-04-06

申请号：US898091

申请日：1997-07-23

申请人： Shinji Yamakawa ,  Koichi Noguchi ,  Shinichiro Wada

发明人： Shinji Yamakawa ,  Koichi Noguchi ,  Shinichiro Wada

IPC分类号： H04N1/10 ,  H04N1/193 ,  H04N1/48 ,  H04N1/46 ,  G03F3/08 ,  G06K9/00

CPC分类号： H04N1/486 ,  H04N1/1013 ,  H04N1/193 ,  H04N2201/04705 ,  H04N2201/04706 ,  H04N2201/04786

摘要： An image reading apparatus includes a reference pattern having slanting lines, which is provided outside a reading range and read by image sensors arranged at separate positions in a sub-scanning direction. A reference-position determining unit detects one of the slanting lines in the reference pattern based on image data output from one of the image sensors so that a position of the image data when one of the slanting lines is detected is determined as a reference position. First and second delay units have line memories which store image data read out from an original image having lines, the delay units delaying outputting of the image data from the line memories line by line. First and second determining units determine image data having color values at imaginary points. An error measurement unit selects one of the imaginary points whose image data has a minimum difference between the color values of the image data. First and second line correcting units output image data having the color values at a corrected position of each picture element by using an interpolation function, the interpolation function having a set of correction factors determined based on a distance between the selected imaginary point and the reference position.

摘要翻译： 图像读取装置包括具有倾斜线的参考图案，该参考图案设置在读取范围之外并且被设置在副扫描方向上的分离位置处的图像传感器读取。 参考位置确定单元基于从一个图像传感器输出的图像数据来检测参考图案中的一个倾斜线，使得当检测到倾斜线之一时的图像数据的位置被确定为参考位置。 第一和第二延迟单元具有线存储器，其存储从具有线的原始图像读出的图像数据，延迟单元延迟从行存储器逐行输出图像数据。 第一和第二确定单元确定在虚拟点处具有颜色值的图像数据。 误差测量单元选择其图像数据在图像数据的颜色值之间具有最小差异的虚数点之一。 第一和第二行校正单元通过使用内插函数输出在每个像素的校正位置具有颜色值的图像数据，该插值函数具有基于所选择的虚点与参考位置之间的距离确定的一组校正因子 。

公开(公告)号：US20110024838A1

公开(公告)日：2011-02-03

申请号：US12834787

申请日：2010-07-12

申请人： Keigo KITAZAWA ,  Junji Noguchi ,  Takayuki Oshima ,  Shinichiro Wada ,  Tomoyuki Miyoshi ,  Atsushi Itoh

发明人： Keigo KITAZAWA ,  Junji Noguchi ,  Takayuki Oshima ,  Shinichiro Wada ,  Tomoyuki Miyoshi ,  Atsushi Itoh

IPC分类号： H01L27/06 ,  H01L29/78

CPC分类号： H01L29/7835 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/41758 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/4238

摘要： There is provided a high withstand voltage LDMOS which is a MOS transistor formed on a semiconductor substrate and isolated by a trench, and a source region of which is sandwiched by a drain region, in which the metal layer gate wire connected to the gate electrode is led out outside the trench so as to pass over a P-type drift layer.

摘要翻译： 提供了一种高耐压LDMOS，其是形成在半导体衬底上并由沟槽隔离的MOS晶体管，其源极区域被漏极区夹在中，其中连接到栅电极的金属层栅极线为 在沟槽外引出，以通过P型漂移层。