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公开(公告)号：US11700004B2
公开(公告)日：2023-07-11
申请号：US17587914
申请日：2022-01-28
发明人： HaiFeng Zhou
CPC分类号： H03K23/005 , H03M7/16
摘要： A bi-directional Gray code counter includes a first set of logic circuitry configured to receive an input having a first sequence of bits representing a first value. The first set of logic circuitry is further configured to convert the first sequence of bits to a second sequence of bits representing the first value. The bi-directional Gray code counter further includes a second set of logic circuitry and third second set of logic circuitry. The second set of logic circuitry is configured to compare the second sequence of bits to a bit index pattern. The third set of logic circuitry is configured to transition one bit in the first sequence of bits from a first state to a second state to form a third sequence of bits representing a second value. The one bit is transitioned in response to the second sequence of bits being compared to the bit index pattern.
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公开(公告)号：US11494192B2
公开(公告)日：2022-11-08
申请号：US16860842
申请日：2020-04-28
发明人： Jiasheng Chen , YunXiao Zou , Bin He , Angel E. Socarras , QingCheng Wang , Wei Yuan , Michael Mantor
摘要： A processing element is implemented in a stage of a pipeline and configured to execute an instruction. A first array of multiplexers is to provide information associated with the instruction to the processing element in response to the instruction being in a first set of instructions. A second array of multiplexers is to provide information associated with the instruction to the first processing element in response to the instruction being in a second set of instructions. A control unit is to gate at least one of power or a clock signal provided to the first array of multiplexers in response to the instruction being in the second set.
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公开(公告)号：US20220196487A1
公开(公告)日：2022-06-23
申请号：US17126326
申请日：2020-12-18
发明人： Lin WANG
摘要： A current control module is employed to protect a conductive feature of a printed circuit board (PCB) from an overcurrent event by comparing a reference voltage output from a compensation circuit connected to a reference power supply to a voltage output from a conductive feature connected to a power supply which is different from the reference power supply. The reference output voltage is representative of an anticipated voltage output from the conductive feature. The current control module is configured to initiate regulation of power to the conductive feature when the voltage output from the conductive feature exceeds the reference voltage output.
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公开(公告)号：US10656951B2
公开(公告)日：2020-05-19
申请号：US15789318
申请日：2017-10-20
发明人： Jiasheng Chen , YunXiao Zou , Bin He , Angel E. Socarras , QingCheng Wang , Wei Yuan , Michael Mantor
摘要： A processing element is implemented in a stage of a pipeline and configured to execute an instruction. A first array of multiplexers is to provide information associated with the instruction to the processing element in response to the instruction being in a first set of instructions. A second array of multiplexers is to provide information associated with the instruction to the first processing element in response to the instruction being in a second set of instructions. A control unit is to gate at least one of power or a clock signal provided to the first array of multiplexers in response to the instruction being in the second set.
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公开(公告)号：US11822956B2
公开(公告)日：2023-11-21
申请号：US17134781
申请日：2020-12-28
发明人： ZhongXiang Luo , JiXin Shan , MingTao Gu
IPC分类号： G06T1/20 , G06T1/60 , G06F9/48 , G06F12/0895
CPC分类号： G06F9/485 , G06F12/0895 , G06T1/20 , G06T1/60
摘要： One or more shader processor inputs (SPIs) provide work items from a thread group for execution on one or more shader engines. A command processor selectively dispatches the work items to the SPIs based on a size of the thread group and a format of cache lines of a cache implemented in the one or more shader engines. The command processor operates in a tile mode in which the command processor schedules the work items in multidimensional blocks that correspond to the format of the cache lines. In some cases, the format of the cache lines is determined by a texture surface format and a swizzle mode for storing texture data. The SPIs (or corresponding drivers) adaptively select wave size, tile size, and wave walk mode based on thread group size, UAV surface format. The SPIs adaptively launch and schedule waves in a thread group based on selected file size, wave walk mode, and wave size to improve cache locality, reduce memory access, and create address pattern to improve memory efficiency.
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公开(公告)号：US20220197679A1
公开(公告)日：2022-06-23
申请号：US17126315
申请日：2020-12-18
发明人： Yinan JIANG , ZhenYu MIN , WenWen TANG
摘要： A processing system includes physical function circuitry to execute virtual functions and a processing unit configured to operate in a first mode that allows more than one virtual function to execute on the physical function circuitry and a second mode that constrains the physical function circuitry to executing a single virtual function. A first virtual function modifies a state of the processing unit in response to the processing unit being in the second mode. A host driver executing on the processing unit modifies an operating mode indicator to indicate that the processing unit is operating in the first mode or to indicate that the processing unit is operating in the second mode. Microcode executing on the processing unit accesses the operating mode indicator to determine whether the processing unit is operating in the first mode or the second mode.
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公开(公告)号：US10198283B2
公开(公告)日：2019-02-05
申请号：US15348225
申请日：2016-11-10
发明人： Jeffrey G. Cheng , Yinan Jiang , Guangwen Yang , Kelly Donald Clark Zytaruk , LingFei Liu , XiaoWei Wang
摘要： A request is sent from a new virtual function (VF) to a physical function for requesting the initialization of the new VF. The controlling physical function and the new VF establish a two-way communication channel that to start and end the VF's exclusive accesses to registers in a configuration space. The physical function uses a timing control to monitor that exclusive register access by the new VF is completed within a predetermined time period. The new VF is only granted a predetermined time period of exclusive access to complete its initialization process. If the exclusive access period is timed out, the controlling physical function can terminate the VF to prevent GPU stalls.
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公开(公告)号：US12061124B2
公开(公告)日：2024-08-13
申请号：US17126326
申请日：2020-12-18
发明人： Lin Wang
CPC分类号： G01K7/22 , H01C7/008 , H05K1/0254 , H05K1/09 , H05K7/06
摘要： A current control module is employed to protect a conductive feature of a printed circuit board (PCB) from an overcurrent event by comparing a reference voltage output from a compensation circuit connected to a reference power supply to a voltage output from a conductive feature connected to a power supply which is different from the reference power supply. The reference output voltage is representative of an anticipated voltage output from the conductive feature. The current control module is configured to initiate regulation of power to the conductive feature when the voltage output from the conductive feature exceeds the reference voltage output.
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公开(公告)号：US11269672B2
公开(公告)日：2022-03-08
申请号：US16399312
申请日：2019-04-30
发明人： Yinan Jiang , Kun Xue
摘要： A processing system detects excessive requests sent on behalf of a virtual machine executing at the processing system within a predetermined period of time and denies subsequent requests sent on behalf of that virtual machine until after the predetermined period of time has elapsed in order to grant access to resources of the processing system for servicing requests from other virtual machines and to prevent a virtual machine that has been compromised by an attack from overwhelming the processing system with malicious requests. The processing system sets a threshold number of event requests for each type of event request that can occur within a predetermined period of time. If the number of event requests of a certain type exceeds the threshold for that event type, the processing system ignores subsequent event requests of that type until the predetermined period of time has expired.
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公开(公告)号：US08994191B2
公开(公告)日：2015-03-31
申请号：US14159813
申请日：2014-01-21
发明人： I-Tseng Lee , Yi Hsiu Liu
CPC分类号： H01L24/17 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/81 , H01L24/83 , H01L25/0657 , H01L2224/0401 , H01L2224/1134 , H01L2224/13082 , H01L2224/131 , H01L2224/13147 , H01L2224/1356 , H01L2224/16113 , H01L2224/16221 , H01L2224/16225 , H01L2224/16227 , H01L2224/17134 , H01L2224/17179 , H01L2224/17515 , H01L2224/17517 , H01L2224/26125 , H01L2224/26155 , H01L2224/29011 , H01L2224/29012 , H01L2224/29019 , H01L2224/2919 , H01L2224/3201 , H01L2224/32057 , H01L2224/32058 , H01L2224/32059 , H01L2224/32225 , H01L2224/73104 , H01L2224/73204 , H01L2224/81191 , H01L2224/81193 , H01L2224/83191 , H01L2224/83193 , H01L2225/06513 , H01L2225/06565 , H01L2924/07025 , H01L2924/15311 , H01L2924/351 , H01L2924/3512 , H01L2924/00014 , H01L2924/00 , H01L2924/014 , H01L2924/00012
摘要： The present invention relates to die-die stacking structure and the method for making the same. The die-die stacking structure comprises a top die having a bottom surface, a first insulation layer covering the bottom surface of the top die, a bottom die having a top surface, a second insulation layer covering the top surface of the bottom die, a plurality of connection members between the top die and the bottom die and a protection material between the first insulation layer and the second insulation layer. The plurality of connection members communicates the top die with the bottom die. The protection material bridges the plurality of connection members to form a mesh layout between the first insulation layer and the second insulation layer. The structure and method of present invention at least provide more strength and stress buffer to resist die warpage and absorb thermal cycling stress, and then prevents the bump and dielectric materials in the die-die stacking structure from cracking caused by thermal stress or external mechanical stress.
摘要翻译： 本发明涉及模片堆叠结构及其制造方法。 模片堆叠结构包括具有底表面的顶模，覆盖顶模的底表面的第一绝缘层，具有顶表面的底模，覆盖底模顶表面的第二绝缘层， 顶模和底模之间的多个连接构件和第一绝缘层与第二绝缘层之间的保护材料。 多个连接构件将顶模与底模连通。 保护材料桥接多个连接构件以在第一绝缘层和第二绝缘层之间形成网格布局。 本发明的结构和方法至少提供更多的强度和应力缓冲以抵抗模翘曲并吸收热循环应力，然后防止模芯堆叠结构中的凸起和介电材料由热应力或外部机械应力引起的破裂 。
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