公开(公告)号：US20120171850A1

公开(公告)日：2012-07-05

申请号：US13394770

申请日：2010-08-24

Applicant: Misako Honaga ,  Takeyoshi Masuda ,  Shin Harada

Inventor： Misako Honaga ,  Takeyoshi Masuda ,  Shin Harada

IPC: H01L21/311

CPC classification number: H01L29/7802 ,  H01L23/544 ,  H01L29/1608 ,  H01L29/66068 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of manufacturing a semiconductor device includes the steps of forming a semiconductor layer made of SiC on an SiC substrate, forming a film on the semiconductor layer, and forming a groove in the film. The semiconductor device including a chip having an interlayer insulating film includes a groove formed in the interlayer insulating film to cross the chip.

Abstract translation: 一种制造半导体器件的方法包括以下步骤：在SiC衬底上形成由SiC制成的半导体层，在半导体层上形成膜，并在膜中形成沟槽。 包括具有层间绝缘膜的芯片的半导体器件包括形成在层间绝缘膜中以跨越芯片的沟槽。

公开(公告)号：US20120149175A1

公开(公告)日：2012-06-14

申请号：US13390869

申请日：2011-02-25

Applicant: Keiji Wada ,  Takeyoshi Masuda ,  Tomihito Miyazaki ,  Toru Hiyoshi ,  Satomi Itoh ,  Hiromu Shiomi

Inventor： Keiji Wada ,  Takeyoshi Masuda ,  Tomihito Miyazaki ,  Toru Hiyoshi ,  Satomi Itoh ,  Hiromu Shiomi

IPC: H01L21/04

CPC classification number: H01L21/02052 ,  H01L21/02057 ,  H01L21/67051 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7802

Abstract: A method of cleaning a SiC semiconductor includes the steps of forming an oxide film at the surface of a SiC semiconductor, and removing the oxide film. At the step of forming an oxide film, an oxide film is formed using ozone water having a concentration greater than or equal to 30 ppm. The forming step preferably includes the step of heating at least one of the surface of the SiC semiconductor and the ozone water. Thus, there can be obtained a method of cleaning a SiC semiconductor that can exhibit cleaning effect on the SiC semiconductor.

Abstract translation: 清洗SiC半导体的方法包括以下步骤：在SiC半导体的表面形成氧化膜，除去氧化物膜。 在形成氧化膜的步骤中，使用浓度大于或等于30ppm的臭氧水形成氧化膜。 成形步骤优选包括加热SiC半导体的表面和臭氧水中的至少一个的步骤。 因此，可以获得能够对SiC半导体具有清洁效果的SiC半导体的清洗方法。

公开(公告)号：US20120126251A1

公开(公告)日：2012-05-24

申请号：US13388691

申请日：2011-02-25

Applicant: Makoto Sasaki ,  Shin Harada ,  Takeyoshi Masuda ,  Keiji Wada ,  Hiroki Inoue ,  Taro Nishiguchi ,  Kyoko Okita ,  Yasuo Namikawa ,  Taku Horii

Inventor： Makoto Sasaki ,  Shin Harada ,  Takeyoshi Masuda ,  Keiji Wada ,  Hiroki Inoue ,  Taro Nishiguchi ,  Kyoko Okita ,  Yasuo Namikawa ,  Taku Horii

IPC: H01L29/24 ,  H01L21/04

CPC classification number: H01L29/7802 ,  H01L21/2007 ,  H01L21/3247 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/66068

Abstract: A method for manufacturing a silicon carbide substrate achieves reduced manufacturing cost. The method includes the steps of: preparing a base substrate and a SiC substrate; fabricating a stacked substrate by stacking the base substrate and the SiC substrate; fabricating a connected substrate by heating the stacked substrate; transferring a void, formed at a connection interface, in a thickness direction of the connected substrate by heating the connected substrate to cause the base substrate to have a temperature higher than that of the SiC substrate; and removing the void by removing a region including a main surface of the base substrate opposite to the SiC substrate.

Abstract translation: 制造碳化硅衬底的方法降低了制造成本。 该方法包括以下步骤：制备基底和SiC衬底; 通过堆叠基底基板和SiC基板来制造堆叠的基板; 通过加热堆叠的基板来制造连接的基板; 通过加热连接的基板，在连接的基板的厚度方向上形成在连接界面处形成的空隙，使得基底基板的温度高于SiC基板的温度; 并且通过去除包括与SiC衬底相对的基底衬底的主表面的区域来去除空隙。

公开(公告)号：US08138504B2

公开(公告)日：2012-03-20

申请号：US12513554

申请日：2007-11-07

Applicant: Shin Harada ,  Takeyoshi Masuda

Inventor： Shin Harada ,  Takeyoshi Masuda

IPC: H01L29/15 ,  H01L21/20

CPC classification number: H01L29/7802 ,  H01L21/02378 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02529 ,  H01L21/02639 ,  H01L21/0445 ,  H01L21/049 ,  H01L29/045 ,  H01L29/0878 ,  H01L29/1608 ,  H01L29/66068

Abstract: A silicon carbide semiconductor device having excellent performance characteristics and a method of manufacturing the same are obtained. A coating film made of Si is formed on an initial growth layer on a 4H—SiC substrate, and an extended terrace surface is formed in a region covered with the coating film. Next, the coating film is removed, and a new growth layer is epitaxially grown on the initial growth layer. A 3C—SiC portion made of 3C—SiC crystals having a polytype stable at a low temperature is grown on the extended terrace surface of the initial growth layer. A channel region of a MOSFET or the like is provided in the 3C—SiC portion having a narrow band gap. As a result, the channel mobility is improved because of a reduction in an interface state, and a silicon carbide semiconductor device having excellent performance characteristics is obtained.

Abstract translation: 获得具有优异性能的碳化硅半导体器件及其制造方法。 在4H-SiC基板上的初始生长层上形成由Si制成的涂膜，并且在涂覆膜覆盖的区域中形成延伸的台阶表面。 接着，除去涂膜，在初始生长层上外延生长新的生长层。 在初始生长层的延伸平台表面上生长由低温下具有多型稳定性的3C-SiC晶体制成的3C-SiC部分。 在具有窄带隙的3C-SiC部分中提供MOSFET等的沟道区域。 结果，由于接口状态的降低，沟道迁移率得到改善，并且获得了具有优异性能的碳化硅半导体器件。

公开(公告)号：US20120056201A1

公开(公告)日：2012-03-08

申请号：US13320243

申请日：2010-04-27

Applicant: Keiji Wada ,  Shin Harada ,  Takeyoshi Masuda ,  Misako Honaga ,  Taro Nishiguchi ,  Makoto Sasaki ,  Shinsuke Fujiwara ,  Yasuo Namikawa

Inventor： Keiji Wada ,  Shin Harada ,  Takeyoshi Masuda ,  Misako Honaga ,  Taro Nishiguchi ,  Makoto Sasaki ,  Shinsuke Fujiwara ,  Yasuo Namikawa

IPC: H01L29/739

CPC classification number: H01L29/7802 ,  C30B23/00 ,  C30B29/36 ,  C30B33/06 ,  H01L21/02378 ,  H01L21/02529 ,  H01L21/2007 ,  H01L29/045 ,  H01L29/0878 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7395

Abstract: An IGBT, which is a vertical type IGBT allowing for reduced on-resistance while restraining defects from being produced, includes: a silicon carbide substrate, a drift layer, a well region, an n+ region, an emitter contact electrode, a gate oxide film, a gate electrode, and a collector electrode. The silicon carbide substrate includes: a base layer made of silicon carbide and having p type conductivity; and a SiC layer made of single-crystal silicon carbide and disposed on the base layer. The base layer has a p type impurity concentration exceeding 1×1018 cm−3.

Abstract translation: IGBT是一种允许在抑制缺陷产生的同时降低导通电阻的垂直型IGBT，包括：碳化硅衬底，漂移层，阱区，n +区，发射极接触电极，栅极氧化膜 ，栅电极和集电极。 碳化硅基板包括：由碳化硅制成并具有p型导电性的基底层; 以及由单晶碳化硅制成并设置在基底层上的SiC层。 基极层的p型杂质浓度超过1×1018cm-3。

公开(公告)号：US20110233562A1

公开(公告)日：2011-09-29

申请号：US13131369

申请日：2010-04-06

Applicant: Shin Harada ,  Makoto Sasaki ,  Takeyoshi Masuda

Inventor： Shin Harada ,  Makoto Sasaki ,  Takeyoshi Masuda

IPC: H01L29/161 ,  H01L21/20

CPC classification number: H01L29/7802 ,  B24B7/17 ,  B24B7/228 ,  B24B37/08 ,  B24B37/10 ,  C30B25/20 ,  C30B29/36 ,  H01L21/02378 ,  H01L21/0243 ,  H01L21/02529 ,  H01L21/0465 ,  H01L29/02 ,  H01L29/045 ,  H01L29/063 ,  H01L29/0657 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/78 ,  H01L29/7813 ,  H01L29/808 ,  H01L29/8083 ,  H01L29/812 ,  H01L29/8122 ,  H01L29/8128 ,  H01L29/8611 ,  H01L29/872

Abstract: A substrate achieving suppressed deterioration of processing accuracy of a semiconductor device due to bending of the substrate, a substrate with a thin film and a semiconductor device formed with the substrate above, and a method of manufacturing the semiconductor device above are obtained. A substrate according to the present invention has a main surface having a diameter of 2 inches or greater, a value for bow at the main surface being not smaller than −40 μm and not greater than −5 μm, and a value for warp at the main surface being not smaller than 5 μm and not greater than 40 μm. Preferably, a value for surface roughness Ra of the main surface of the substrate is not greater than 1 nm and a value for surface roughness Ra of a main surface is not greater than 100 nm.

Abstract translation: 获得由于基板的弯曲，具有薄膜的基板和形成有上述基板的半导体器件导致的半导体器件的加工精度的抑制劣化的基板，以及上述制造半导体器件的方法。 根据本发明的基板具有直径为2英寸或更大的主表面，主表面上的弓形值不小于-40μm且不大于-5μm，并且在该表面处的翘曲值 主表面不小于5μm，不大于40μm。 优选地，基板的主表面的表面粗糙度Ra的值不大于1nm，并且主表面的表面粗糙度Ra的值不大于100nm。

公开(公告)号：US07981709B2

公开(公告)日：2011-07-19

申请号：US12593130

申请日：2008-03-10

Applicant: Takeyoshi Masuda

Inventor： Takeyoshi Masuda

IPC: H01L21/00 ,  H01L21/8242 ,  H01L21/336

CPC classification number: H01L21/02433 ,  C30B29/36 ,  C30B33/02 ,  H01L21/02378 ,  H01L21/02447 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/046 ,  H01L21/0475 ,  H01L21/3247 ,  H01L21/8213 ,  H01L29/0657 ,  H01L29/1037 ,  H01L29/1608 ,  H01L29/66068

Abstract: A method for fabricating a semiconductor device includes the steps of forming a SiC film, forming trenches at a surface of the SiC film, heat-treating the SiC film with silicon supplied to the surface of the SiC film, and obtaining a plurality of macrosteps to constitute channels, at the surface of the SiC film by the step of heat-treating. Taking the length of one cycle of the trenches as L and the height of the trenches as h, a relation L=h(cot α+cot β) (where α and β are variables that satisfy the relations 0.5≦α, β≦45) holds between the length L and the height h. Consequently, the semiconductor device can be improved in property.

Abstract translation: 一种制造半导体器件的方法包括以下步骤：形成SiC膜，在SiC膜的表面形成沟槽，用提供给SiC膜表面的硅对SiC膜进行热处理，并获得多个宏步骤 通过热处理步骤在SiC膜的表面构成通道。 将沟槽的一个周期的长度作为L和沟槽的高度为h，关系L = h（cotα+ cot＆bgr）（其中α和＆bgr是满足关系0.5＆nlE;α， ＆bgr;＆nlE; 45）保持在长度L和高度h之间。 因此，可以提高半导体器件的性能。

公开(公告)号：US07867882B2

公开(公告)日：2011-01-11

申请号：US12444551

申请日：2007-08-13

Applicant: Kazuhiro Fujikawa ,  Takeyoshi Masuda

Inventor： Kazuhiro Fujikawa ,  Takeyoshi Masuda

IPC: H01L21/265

CPC classification number: H01L29/808 ,  H01L21/0465 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66901 ,  Y10S438/931

Abstract: A method of manufacturing an SiC semiconductor device includes the steps of ion implanting a dopant at least in a part of a surface of an SiC single crystal, forming an Si film on the surface of the ion-implanted SiC single crystal, and heating the SiC single crystal on which the Si film is formed to a temperature not less than a melting temperature of the Si film.

Abstract translation: 一种制造SiC半导体器件的方法包括以下步骤：在SiC单晶的至少一部分表面上离子注入掺杂剂，在离子注入的SiC单晶的表面上形成Si膜，并加热SiC 在其上形成Si膜的单晶，其温度不低于Si膜的熔融温度。

公开(公告)号：US20100127278A1

公开(公告)日：2010-05-27

申请号：US12593130

申请日：2008-03-10

Applicant: Takeyoshi Masuda

Inventor： Takeyoshi Masuda

IPC: H01L29/161 ,  H01L21/04

CPC classification number: H01L21/02433 ,  C30B29/36 ,  C30B33/02 ,  H01L21/02378 ,  H01L21/02447 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/046 ,  H01L21/0475 ,  H01L21/3247 ,  H01L21/8213 ,  H01L29/0657 ,  H01L29/1037 ,  H01L29/1608 ,  H01L29/66068

Abstract: A method for fabricating a semiconductor device includes the steps of forming a SiC film, forming trenches at a surface of the SiC film, heat-treating the SiC film with silicon supplied to the surface of the SiC film, and obtaining a plurality of macrosteps to constitute channels, at the surface of the SiC film by the step of heat-treating. Taking the length of one cycle of the trenches as L and the height of the trenches as h, a relation L=h(cot α+cot β) (where α and β are variables that satisfy the relations 0.5≦α,β,≦45) holds between the length L and the height h. Consequently, the semiconductor device can be improved in property.

Abstract translation: 一种制造半导体器件的方法包括以下步骤：形成SiC膜，在SiC膜的表面形成沟槽，用提供给SiC膜表面的硅对SiC膜进行热处理，并获得多个宏步骤 通过热处理步骤在SiC膜的表面构成通道。 将沟槽的一个周期的长度作为L和沟槽的高度为h，关系L = h（cotα+ cot＆bgr）（其中α和＆bgr是满足关系0.5＆nlE;α， ＆bgr;，＆nlE; 45）保持在长度L和高度h之间。 因此，可以提高半导体器件的性能。