公开(公告)号：US20220406730A1

公开(公告)日：2022-12-22

申请号：US17350317

申请日：2021-06-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Po-Chen LAI ,  Chin-Hua WANG ,  Ming-Chih YEW ,  Che-Chia YANG ,  Shu-Shen YEH ,  Po-Yao LIN ,  Shin-Puu JENG

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/065 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56

摘要： A package structure is provided. The package structure includes a redistribution structure and a semiconductor die over the redistribution structure, and bonding elements below the redistribution structure. The semiconductor die has a first sidewall and a second sidewall connected to each other. The bonding elements include a first row of bonding elements and a second row of bonding elements. In a plan view, the second row of bonding elements is arranged between the first row of bonding elements and an extending line of the second sidewall. A minimum distance between the second row of bonding elements and the first sidewall is greater than the minimum distance between the first row of bonding elements and the first sidewall.

公开(公告)号：US20220367312A1

公开(公告)日：2022-11-17

申请号：US17527831

申请日：2021-11-16

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Po-Chen LAI ,  Ming-Chih YEW ,  Po-Yao LIN ,  Chin-Hua WANG ,  Shin-Puu JENG

IPC分类号： H01L23/367 ,  H01L25/065 ,  H01L21/48 ,  H01L23/498

摘要： A semiconductor package structure is provided. The semiconductor package structure includes a carrier substrate, an interposer substrate, a semiconductor device, a lid, and a thermal interface material. The interposer substrate is disposed on the carrier substrate. The semiconductor device is disposed on the interposer substrate. The lid is disposed on the carrier substrate to cover the semiconductor device. The thermal interface material is disposed between the lid and the semiconductor device. A first recess is formed on a lower surface of the lid facing the semiconductor device, and the first recess overlaps the semiconductor device in a top view.

公开(公告)号：US20220359320A1

公开(公告)日：2022-11-10

申请号：US17814874

申请日：2022-07-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shin-Puu JENG ,  Feng-Cheng HSU ,  Shuo-Mao CHEN

IPC分类号： H01L23/13 ,  H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L25/00

摘要： A package structure and a method of forming the same are provided. The package structure includes a package substrate, an interposer substrate, a first semiconductor device, and a second semiconductor device. The interposer substrate is disposed over the package substrate and includes a silicon substrate. The interposer substrate has a bottom surface facing and adjacent to the package substrate, a top surface opposite the bottom surface, and a cavity formed on the top surface. The first semiconductor device is disposed on the top surface of the interposer substrate. The second semiconductor device is received in the cavity and electrically connected to the first semiconductor device and/or the interposer substrate.

公开(公告)号：US20220336377A1

公开(公告)日：2022-10-20

申请号：US17856175

申请日：2022-07-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shu-Shen YEH ,  Chin-Hua WANG ,  Kuang-Chun LEE ,  Po-Yao LIN ,  Shyue-Ter LEU ,  Shin-Puu JENG

IPC分类号： H01L23/00 ,  H01L23/04 ,  H01L23/10 ,  H01L23/367

摘要： A chip package is provided. The chip package includes a substrate and a semiconductor chip over the substrate. The chip package also includes an upper plate extending across edges of the semiconductor chip. The chip package further includes a first support structure connecting a first corner portion of the substrate and a first corner of the upper plate. In addition, the chip package includes a second support structure connecting a second corner portion of the substrate and a second corner of the upper plate. The upper plate has a side edge connecting the first support structure and the second support structure, and the side edge extends across opposite edges of the semiconductor chip.

公开(公告)号：US20220310468A1

公开(公告)日：2022-09-29

申请号：US17838434

申请日：2022-06-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Meng-Liang LIN ,  Po-Hao TSAI ,  Po-Yao CHUANG ,  Yi-Wen WU ,  Techi WONG ,  Shin-Puu JENG

IPC分类号： H01L23/31 ,  H01L23/498 ,  H01L23/24 ,  H01L23/00 ,  H01L25/16 ,  H01L25/065 ,  H01L25/18 ,  H01L21/56 ,  H01L21/48

摘要： A package structure is provided. The package structure includes a redistribution structure, and the redistribution structure has multiple insulating layers and multiple conductive features. The package structure also includes a semiconductor die and a device element over opposite surfaces of the redistribution structure. The package structure further includes a first protective layer at least partially surrounding the semiconductor die. In addition, the package structure includes a second protective layer at least partially surrounding the device element. The second protective layer is thicker than the first protective layer, and the second protective layer and the first protective layer have different coefficients of thermal expansion.

公开(公告)号：US20220181232A1

公开(公告)日：2022-06-09

申请号：US17679372

申请日：2022-02-24

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shin-Puu JENG ,  Po-Yao LIN ,  Feng-Cheng HSU ,  Shuo-Mao CHEN ,  Chin-Hua WANG

IPC分类号： H01L23/367 ,  H01L21/48 ,  H01L25/00 ,  H01L25/18 ,  H01L21/56

摘要： A method for forming a package structure is provided, including forming an interconnect structure over a carrier substrate and forming a semiconductor die over a first side of the interconnect structure. A removable film is formed over the semiconductor die. The method includes forming a first stacked die package structure over the first side of the interconnect structure. A top surface of the removable film is higher than a top surface of the first stacked die package structure. The method includes forming a package layer, removing a portion of the package layer to expose a portion of the removable film, removing the removable film to form a recess, forming a lid structure over the semiconductor die and the first stacked die package structure. The lid structure has a main portion and a protruding portion disposed in the recess and extending from the main portion.

公开(公告)号：US20220108967A1

公开(公告)日：2022-04-07

申请号：US17554475

申请日：2021-12-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shin-Puu JENG ,  Shuo-Mao CHEN ,  Feng-Cheng HSU

IPC分类号： H01L23/00 ,  H01L25/065 ,  H01L21/56 ,  H01L25/10 ,  H01L25/00 ,  H01L21/683 ,  H01L23/31

摘要： A chip package structure is provided. The chip package structure includes a first redistribution structure having a first surface and a second surface opposite to the first surface. The chip package structure includes a first chip over the first surface. The chip package structure includes a first conductive bump connected between the first chip and the first redistribution structure. The chip package structure includes a first conductive pillar over the first surface and electrically connected to the first redistribution structure. The chip package structure includes a second chip over the second surface. The chip package structure includes a second conductive bump connected between the second chip and the first redistribution structure. The chip package structure includes a second conductive pillar over the second surface and electrically connected to the first redistribution structure.

公开(公告)号：US20210098379A1

公开(公告)日：2021-04-01

申请号：US17121051

申请日：2020-12-14

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shin-Puu JENG ,  Shuo-Mao CHEN ,  Feng-Cheng HSU ,  Po-Yao LIN

IPC分类号： H01L23/538 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L21/78 ,  H01L23/31 ,  H01L25/16

摘要： A method for forming a chip package structure is provided. The method includes forming a first redistribution structure over a first carrier substrate. The method includes bonding a chip structure to the first surface through a first conductive bump. The method includes forming a first molding layer over the first redistribution structure. The method includes removing the first carrier substrate. The method includes forming a second conductive bump over the second surface. The method includes forming a second redistribution structure over a second carrier substrate. The method includes bonding the first redistribution structure to the third surface. The method includes forming a second molding layer over the second redistribution structure. The method includes removing the second carrier substrate. The method includes removing a portion of the second redistribution structure from the fourth surface. The method includes forming a third conductive bump over the fourth surface.

公开(公告)号：US20150235873A1

公开(公告)日：2015-08-20

申请号：US14705555

申请日：2015-05-06

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Wei-Cheng WU ,  Shang-Yun HOU ,  Shin-Puu JENG ,  Chen-Hua YU

IPC分类号： H01L21/56 ,  H01L21/768 ,  H01L25/00 ,  H01L25/065 ,  H01L21/48 ,  H01L23/00

CPC分类号： H01L23/49827 ,  H01L21/486 ,  H01L21/565 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49833 ,  H01L24/11 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05573 ,  H01L2224/11002 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/01019 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/381 ,  H01L2924/00 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05684

摘要： A method of manufacturing a package system includes forming a first interconnect structure over a first surface of a first substrate, forming at least one first through silicon via (TSV) structure in the first substrate, disposing the first substrate over a carrier with the first surface facing the carrier, depositing a molding compound material over the carrier and around the first substrate, forming a second interconnect structure over a second surface of the first substrate, removing the carrier to expose the first interconnect structure over the first surface of the first substrate, and disposing a first integrated circuit over the first surface of the first substrate. The first integrated circuit is electrically coupled with the at least one first TSV structure through the first interconnect structure and connecting bumps.

摘要翻译： 制造封装系统的方法包括在第一衬底的第一表面上形成第一互连结构，在第一衬底中形成至少一个第一穿透硅通孔（TSV）结构，将第一衬底设置在载体上，第一表面 面向载体，在载体上并围绕第一基底沉积模塑复合材料，在第一基底的第二表面上形成第二互连结构，去除载体以在第一基底的第一表面上露出第一互连结构， 以及在所述第一基板的所述第一表面上设置第一集成电路。 第一集成电路通过第一互连结构和连接凸块与至少一个第一TSV结构电耦合。

公开(公告)号：US20140130962A1

公开(公告)日：2014-05-15

申请号：US14157210

申请日：2014-01-16

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chen-Hua YU ,  Kuo-Ching HSU ,  Chen-Shien CHEN ,  Ching-Wen HSIAO ,  Wen-Chih CHIOU ,  Shin-Puu JENG ,  Hung-Jung TU

IPC分类号： H01L21/02

CPC分类号： H01L21/02057 ,  H01L21/187 ,  H01L21/2007 ,  H01L21/6835 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/68381 ,  Y10T156/10 ,  Y10T156/1153 ,  Y10T156/1158

摘要： A method includes receiving a carrier with a release layer formed thereon. A first adhesive layer is formed on a wafer. A second adhesive layer is formed over the first adhesive layer or over the release layer. The carrier and the wafer are bonded with the release layer, the first adhesive layer, and the second adhesive layer in between the carrier and the wafer.

摘要翻译： 一种方法包括接收其上形成有释放层的载体。 第一粘合剂层形成在晶片上。 第二粘合剂层形成在第一粘合剂层上或剥离层上方。 载体和晶片与载体和晶片之间的剥离层，第一粘合剂层和第二粘合剂层结合。