公开(公告)号：US11735594B2

公开(公告)日：2023-08-22

申请号：US17341142

申请日：2021-06-07

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Tzer-Min Shen ,  Zhiqiang Wu ,  Chung-Cheng Wu ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang ,  Min Cao

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L29/786 ,  H01L27/12 ,  H01L21/762 ,  H01L21/84 ,  H01L29/423 ,  H01L29/10 ,  H01L29/78 ,  H01L29/06 ,  H01L29/04

CPC分类号： H01L27/1207 ,  H01L21/76275 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/785 ,  H01L29/7869 ,  H01L21/823878 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/7853

摘要： The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first fin active region of a first semiconductor material disposed within the first region, oriented in a first direction, wherein the first fin active region has a crystalline direction along the first direction; and a second fin active region of a second semiconductor material disposed within the second region and oriented in the first direction, wherein the second fin active region has a crystalline direction along the first direction.

公开(公告)号：US11735587B2

公开(公告)日：2023-08-22

申请号：US17510014

申请日：2021-10-25

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-Xuan Huang ,  Ching-Wei Tsai ,  Jam-Wem Lee ,  Kuo-Ji Chen ,  Kuan-Lun Cheng

IPC分类号： H01L27/088 ,  H01L29/66 ,  H01L29/417 ,  H01L29/06 ,  H01L27/07 ,  H01L29/78

CPC分类号： H01L27/0886 ,  H01L27/0727 ,  H01L29/0653 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

摘要： The present disclosure provides embodiments of semiconductor devices. A semiconductor device according to the present disclosure include an elongated semiconductor member surrounded by an isolation feature and extending lengthwise along a first direction, a first source/drain feature and a second source/drain feature over a top surface of the elongated semiconductor member, a vertical stack of channel members each extending lengthwise between the first source/drain feature and the second source/drain feature along the first direction, a gate structure wrapping around each of the channel members, an epitaxial layer deposited on the bottom surface of the elongated semiconductor member, a silicide layer disposed on the epitaxial layer, and a conductive layer disposed on the silicide layer.

公开(公告)号：US11699742B2

公开(公告)日：2023-07-11

申请号：US17199877

申请日：2021-03-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Cheng-Ting Chung ,  Kuan-Lun Cheng

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L21/8234

CPC分类号： H01L29/66795 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/7851

摘要： A method includes providing a structure having a frontside and a backside, the structure including a substrate, two or more semiconductor channel layers over the substrate and connecting a first source/drain (S/D) feature and a second S/D feature, and a gate structure engaging the semiconductor channel layers, wherein the substrate is at the backside of the structure and the gate structure is at the frontside of the structure; recessing the first S/D feature, thereby exposing a terminal end of one of the semiconductor channel layers; and depositing a dielectric layer on the first S/D feature and covering the exposed terminal end of the one of the semiconductor channel layers.

公开(公告)号：US11699733B2

公开(公告)日：2023-07-11

申请号：US17397099

申请日：2021-08-09

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Cheng-Ting Chung ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC分类号： H01L29/423 ,  H01L29/66 ,  H01L27/088 ,  H01L29/78 ,  H01L21/8234

CPC分类号： H01L29/42392 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

摘要： A semiconductor device and a method of forming the same are provided. The semiconductor device includes a first gate-all-around (GAA) transistor over a first region of a substrate and a second GAA transistor over a second region of the substrate. The first GAA transistor includes a plurality of first channel members stacked along a first direction vertical to a top surface of the substrate and a first gate structure over the plurality of first channel members. The second GAA transistor includes a plurality of second channel members stacked along a second direction parallel to the top surface of the substrate and a second gate structure over the plurality of second channel members. The plurality of first channel members and the plurality of second channel members comprise a semiconductor material having a first crystal plane and a second crystal plane different from the first crystal plane. The first direction is normal to the first crystal plane and the second direction is normal to the second crystal plane.

公开(公告)号：US11664451B2

公开(公告)日：2023-05-30

申请号：US17216241

申请日：2021-03-29

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kai-Chieh Yang ,  Li-Yang Chuang ,  Pei-Yu Wang ,  Wei Ju Lee ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC分类号： H01L29/78 ,  H01L29/08 ,  H01L27/092 ,  H01L21/8238

CPC分类号： H01L29/7843 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L27/0924 ,  H01L29/0847

摘要： A semiconductor device and a method of forming the same are provided. A semiconductor device according to an embodiment includes a P-type field effect transistor (PFET) and an N-type field effect transistor (NFET). The PFET includes a first gate structure formed over a substrate, a first spacer disposed on a sidewall of the first gate structure, and an unstrained spacer disposed on a sidewall of the first spacer. The NET includes a second gate structure formed over the substrate, the first spacer disposed on a sidewall of the second gate structure, and a strained spacer disposed on a sidewall of the first spacer.

公开(公告)号：US20230113266A1

公开(公告)日：2023-04-13

申请号：US18053236

申请日：2022-11-07

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kuo-Cheng Chiang ,  Shi Ning Ju ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC分类号： H01L27/092 ,  H01L21/308 ,  H01L27/12 ,  H01L21/84 ,  H01L21/762 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/66

摘要： A method includes etching a hybrid substrate to form a recess extending into the hybrid substrate. The hybrid substrate includes a first semiconductor layer having a first surface orientation, a dielectric layer over the first semiconductor layer, and a second semiconductor layer having a second surface orientation different from the first surface orientation. After the etching, a top surface of the first semiconductor layer is exposed to the recess. A spacer is formed on a sidewall of the recess. The spacer contacts a sidewall of the dielectric layer and a sidewall of the second semiconductor layer. An epitaxy is performed to grow an epitaxy semiconductor region from the first semiconductor layer. The spacer is removed.

公开(公告)号：US11621323B2

公开(公告)日：2023-04-04

申请号：US17135623

申请日：2020-12-28

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kuo-Cheng Ching ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC分类号： H01L29/06 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/66 ,  H01L29/49 ,  H01L29/51

摘要： A semiconductor device includes a substrate, an isolation feature over the substrate, a first device fin protruding from the substrate and through the isolation feature, and a second device fin protruding from the substrate and through the isolation feature. The semiconductor device also includes a dielectric fin disposed between the first and second device fins and a metal gate stack engaging the first and second device fins. The dielectric fin separates the metal gate stack into first and second segments and provides electrical isolation between the first and second segments. A portion of the isolation feature is directly under a bottom surface of the dielectric fin.

公开(公告)号：US11588050B2

公开(公告)日：2023-02-21

申请号：US17112293

申请日：2020-12-04

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Li-Zhen Yu ,  Huan-Chieh Su ,  Lin-Yu Huang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC分类号： H01L29/76 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L21/02

摘要： A semiconductor structure and a method of forming the same are provided. In an embodiment, a semiconductor structure includes an epitaxial source feature and an epitaxial drain feature, a vertical stack of channel members disposed over a backside dielectric layer, the vertical stack of channel members extending between the epitaxial source feature and the epitaxial drain feature along a direction, a gate structure wrapping around each of the vertical stack of channel members, and a backside source contact disposed in the backside dielectric layer. The backside source contact includes a top portion adjacent the epitaxial source feature and a bottom portion away from the epitaxial source feature. The top portion and the bottom portion includes a step width change along the direction.

公开(公告)号：US11581436B2

公开(公告)日：2023-02-14

申请号：US17113821

申请日：2020-12-07

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chi-Hsing Hsu ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang ,  Sai-Hooi Yeong

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L29/06

摘要： A semiconductor device includes a substrate. The semiconductor device includes a dielectric layer disposed over a portion of the substrate. The semiconductor device includes a diffusion blocking layer disposed over the dielectric layer. The diffusion blocking layer and the dielectric layer have different material compositions. The semiconductor device includes a ferroelectric layer disposed over the diffusion blocking layer.

公开(公告)号：US11532735B2

公开(公告)日：2022-12-20

申请号：US16890803

申请日：2020-06-02

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kuo-Cheng Chiang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC分类号： H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/165 ,  H01L29/417 ,  H01L29/161 ,  H01L29/78

摘要： Semiconductor structures including active fin structures, dummy fin structures, epitaxy layers, a Ge containing oxide layer and methods of manufacture thereof are described. By implementing the Ge containing oxide layer on the surface of the epitaxy layers formed on the source/drain regions of some of the FinFET devices, a self-aligned epitaxy process is enabled. By implementing dummy fin structures and a self-aligned etch, both the epitaxy layers and metal gate structures from adjacent FinFET devices are isolated in a self-aligned manner.