公开(公告)号：US20210202396A1

公开(公告)日：2021-07-01

申请号：US16932364

申请日：2020-07-17

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jiun Yi Wu ,  Chen-Hua Yu

IPC分类号： H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L25/18 ,  H01L25/00 ,  H01L21/48

摘要： Semiconductor devices and methods of forming the semiconductor devices are described herein that are directed towards the formation of a system on integrated substrate (SoIS) package. The SoIS package includes an integrated fan out structure and a device redistribution structure for external connection to a plurality of semiconductor devices. The integrated fan out structure includes a plurality of local interconnect devices that electrically couple two of the semiconductor devices together. In some cases, the local interconnect device may be a silicon bus, a local silicon interconnect, an integrated passive device, an integrated voltage regulator, or the like. The integrated fan out structure may be fabricated in wafer or panel form and then singulated into multiple integrated fan out structures. The SoIS package may also include an interposer connected to the integrated fan out structure for external connection to the SoIS package.

公开(公告)号：US20210082827A1

公开(公告)日：2021-03-18

申请号：US17107181

申请日：2020-11-30

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jiun Yi Wu ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Chien-Hsun Lee

IPC分类号： H01L23/538 ,  H01L23/31 ,  H01L25/18 ,  H01L21/56 ,  H01L23/00

摘要： A method of forming a semiconductor device includes arranging a semi-finished substrate, which has been tested and is known to be good, on a carrier substrate. Encapsulating the semi-finished substrate in a first encapsulant and arranging at least one semiconductor die over the semi-finished substrate. Electrically coupling at least one semiconductor component of the at least one semiconductor die to the semi-finished substrate and encasing the at least one semiconductor die and portions of the first encapsulant in a second encapsulant. Removing the carrier substrate from the semi-finished substrate and bonding a plurality of external contacts to the semi-finished substrate.

公开(公告)号：US09460977B2

公开(公告)日：2016-10-04

申请号：US14968066

申请日：2015-12-14

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jiun Yi Wu

IPC分类号： H01L23/48 ,  H01L23/31 ,  H01L25/065 ,  H01L23/00 ,  H01L25/10 ,  H01L23/13 ,  H01L21/683 ,  H01L23/498 ,  H01L21/56 ,  H01L25/00

CPC分类号： H01L23/3121 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/3114 ,  H01L23/48 ,  H01L23/481 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/19 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An interposer includes a core dielectric material, a conductive pipe penetrating through the core dielectric material, and a metal pad underlying the conductive pipe. The metal pad includes a center portion overlapped by a region encircled by the conductive pipe, and an outer portion in contact with the conductive pipe. A dielectric layer is underlying the core dielectric material and the metal pad. A via is in the dielectric layer, wherein the via is in physical contact with the center portion of the metal pad.

摘要翻译： 插入器包括芯介电材料，穿透芯介质材料的导电管和导电管下面的金属垫。 金属焊盘包括与由导电管包围的区域重叠的中心部分和与导电管接触的外部部分。 电介质层位于芯介质材料和金属垫的下面。 通孔在电介质层中，其中通孔与金属焊盘的中心部分物理接触。

公开(公告)号：US12100672B2

公开(公告)日：2024-09-24

申请号：US17813906

申请日：2022-07-20

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jiun Yi Wu ,  Chen-Hua Yu

IPC分类号： H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/14 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538

CPC分类号： H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/145 ,  H01L23/3185 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5381 ,  H01L2221/68372

摘要： A device includes an interconnect device attached to a redistribution structure, wherein the interconnect device includes conductive routing connected to conductive connectors disposed on a first side of the interconnect device, a molding material at least laterally surrounding the interconnect device, a metallization pattern over the molding material and the first side of the interconnect device, wherein the metallization pattern is electrically connected to the conductive connectors, first external connectors connected to the metallization pattern, and semiconductor devices connected to the first external connectors.

公开(公告)号：US20240264388A1

公开(公告)日：2024-08-08

申请号：US18164310

申请日：2023-02-03

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shih Wei Liang ,  Yu-Ming Chou ,  Nien-Fang Wu ,  Jiun Yi Wu

IPC分类号： G02B6/42 ,  H01L25/16

CPC分类号： G02B6/4214 ,  H01L25/167

摘要： Package devices and methods of manufacture are discussed. In an embodiment, a method of manufacturing an integrated circuit device includes: forming an optical device layer; forming an optical layer on the optical device layer; after the forming the optical layer, forming a first opening in the optical layer; and embedding a reflective structure in the first opening.

公开(公告)号：US20240258187A1

公开(公告)日：2024-08-01

申请号：US18631966

申请日：2024-04-10

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chien-Hsun Chen ,  Yu-Ling Tsai ,  Jiun Yi Wu ,  Chien-Hsun Lee ,  Chung-Shi Liu

IPC分类号： H01L23/31 ,  H01L23/498 ,  H01L23/538

CPC分类号： H01L23/3121 ,  H01L23/49827 ,  H01L23/5384

摘要： In an embodiment, a device includes: a first integrated circuit die having a first contact region and a first non-contact region; an encapsulant contacting sides of the first integrated circuit die; a dielectric layer contacting the encapsulant and the first integrated circuit die, the dielectric layer having a first portion over the first contact region, a second portion over the first non-contact region, and a third portion over a portion of the encapsulant; and a metallization pattern including: a first conductive via extending through the first portion of the dielectric layer to contact the first integrated circuit die; and a conductive line extending along the second portion and third portion of the dielectric layer, the conductive line having a straight portion along the second portion of the dielectric layer and a first meandering portion along the third portion of the dielectric layer.

公开(公告)号：US20240258185A1

公开(公告)日：2024-08-01

申请号：US18632642

申请日：2024-04-11

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jiun Yi Wu ,  Chen-Hua Yu ,  Chung-Shi Liu

IPC分类号： H01L23/31 ,  H01L21/56

CPC分类号： H01L23/3114 ,  H01L21/568

摘要： A method includes placing a package component over a carrier. The package component includes a device die. A core frame is placed over the carrier. The core frame forms a ring encircling the package component. The method further includes encapsulating the core frame and the package component in an encapsulant, forming redistribution lines over the core frame and the package component, and forming electrical connectors over and electrically coupling to the package component through the redistribution lines.

公开(公告)号：US20240234302A1

公开(公告)日：2024-07-11

申请号：US18617530

申请日：2024-03-26

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chung-Shi Liu ,  Chien-Hsun Lee ,  Jiun Yi Wu ,  Hao-Cheng Hou ,  Hung-Jen Lin ,  Jung Wei Cheng ,  Tsung-Ding Wang ,  Yu-Min Liang ,  Li-Wei Chou

IPC分类号： H01L23/522 ,  H01L21/56 ,  H01L21/683 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC分类号： H01L23/5226 ,  H01L21/563 ,  H01L21/566 ,  H01L21/6835 ,  H01L21/76816 ,  H01L23/3157 ,  H01L23/49822 ,  H01L24/09 ,  H01L24/81 ,  H01L23/49816 ,  H01L24/13 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/02331 ,  H01L2224/13101 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/18161

摘要： An embodiment semiconductor package includes a bare semiconductor chip, a packaged semiconductor chip adjacent the bare semiconductor chip, and a redistribution structure bonded to the bare semiconductor chip and the packaged semiconductor chip. The redistribution structure includes a first redistribution layer having a first thickness; a second redistribution layer having a second thickness; and a third redistribution layer between the first redistribution layer and the second redistribution layer. The third redistribution layer has a third thickness greater than the first thickness and the second thickness. The package further includes an underfill disposed between the bare semiconductor chip and the redistribution structure and a molding compound encapsulating the bare semiconductor chip, the packaged semiconductor chip, and the underfill.

公开(公告)号：US20240136299A1

公开(公告)日：2024-04-25

申请号：US18401928

申请日：2024-01-02

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wei-Yu Chen ,  Chun-Chih Chuang ,  Kuan-Lin Ho ,  Yu-Min Liang ,  Jiun Yi Wu

IPC分类号： H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/20 ,  H01L2221/68372 ,  H01L2224/214 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/19106

摘要： A package includes an interposer structure free of any active devices. The interposer structure includes an interconnect device; a dielectric film surrounding the interconnect device; and first metallization pattern bonded to the interconnect device. The package further includes a first device die bonded to an opposing side of the first metallization pattern as the interconnect device and a second device die bonded to a same side of the first metallization pattern as the first device die. The interconnect device electrically connects the first device die to the second device die.

公开(公告)号：US11955442B2

公开(公告)日：2024-04-09

申请号：US18174784

申请日：2023-02-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jiun Yi Wu ,  Chen-Hua Yu ,  Chung-Shi Liu

IPC分类号： H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC分类号： H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/1427 ,  H01L2924/1437 ,  H01L2924/19103 ,  H01L2924/3511

摘要： In an embodiment, a structure includes a core substrate, a redistribution structure coupled, the redistribution structure including a plurality of redistribution layers, the plurality of redistribution layers comprising a dielectric layer and a metallization layer, a first local interconnect component embedded in a first redistribution layer of the plurality of redistribution layers, the first local interconnect component comprising conductive connectors, the conductive connectors being bonded to a metallization pattern of the first redistribution layer, the dielectric layer of the first redistribution layer encapsulating the first local interconnect component, a first integrated circuit die coupled to the redistribution structure, a second integrated circuit die coupled to the redistribution structure, an interconnect structure of the first local interconnect component electrically coupling the first integrated circuit die to the second integrated circuit die, and a set of conductive connectors coupled to a second side of the core substrate.