公开(公告)号：US20220012400A1

公开(公告)日：2022-01-13

申请号：US16926026

申请日：2020-07-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Shuo Liu ,  Chih-Chun Hsia ,  Hsin Ting Chou ,  Kuanhua Su ,  William Weilun Hong ,  Chih Hung Chen ,  Kei-Wei Chen

IPC: G06F30/392 ,  G06T7/00

Abstract: A method includes cropping a plurality of images from a layout of an integrated circuit, generating a first plurality of hash values, each from one of the plurality of images, loading a second plurality of hash values stored in a hotspot library, and comparing each of the first plurality of hash values with each of the second plurality of hash values. The step of comparing includes calculating a similarity value between the each of the first plurality of hash values and the each of the second plurality of hash values. The method further includes comparing the similarity value with a pre-determined threshold similarity value, and in response to a result that the similarity value is greater than the pre-determined threshold similarity value, recording a position of a corresponding image that has the result. The position is the position of the corresponding image in the layout.

公开(公告)号：US20210366715A1

公开(公告)日：2021-11-25

申请号：US17396948

申请日：2021-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ta-Chun Ma ,  Yi-Cheng Li ,  Pin-Ju Liang ,  Cheng-Po Chau ,  Jung-Jen Chen ,  Pei-Ren Jeng ,  Chii-Horng Li ,  Kei-Wei Chen ,  Cheng-Hsiung Yen

IPC: H01L21/223 ,  H01L29/66 ,  H01L21/311 ,  H01L21/324 ,  H01L21/8238 ,  H01L29/78 ,  H01L27/092

Abstract: In an embodiment, a method includes: forming a first fin extending from a substrate, the substrate including silicon, the first fin including silicon germanium; forming an isolation region around the first fin, an oxide layer being formed on the first fin during formation of the isolation region; removing the oxide layer from the first fin with a hydrogen-based etching process, silicon at a surface of the first fin being terminated with hydrogen after the hydrogen-based etching process; desorbing the hydrogen from the silicon at the surface of the first fin to depassivate the silicon; and exchanging the depassivated silicon at the surface of the first fin with germanium at a subsurface of the first fin.

公开(公告)号：US20210313190A1

公开(公告)日：2021-10-07

申请号：US17353222

申请日：2021-06-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hao Kung ,  Tung-Kai Chen ,  Chih-Chieh Chang ,  Kao-Feng Liao ,  Hui-Chi Huang ,  Kei-Wei Chen

IPC: H01L21/321 ,  H01L21/768 ,  C09G1/02 ,  C09G1/04 ,  H01L21/306

Abstract: Methods of manufacturing a chemical-mechanical polishing (CMP) slurry and methods of performing CMP process on a substrate comprising metal features are described herein. The CMP slurry may be manufactured using a balanced concentration ratio of chelator additives to inhibitor additives, the ratio being determined based on an electro potential (Ev) value of a metal material of the substrate. The CMP process may be performed on the substrate based on the balanced concentration ratio of chelator additives to inhibitor additives of the CMP slurry.

公开(公告)号：US20210272798A1

公开(公告)日：2021-09-02

申请号：US16807086

申请日：2020-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ssutzu Chen ,  Gin-Chen Huang ,  Ya-Ting Tsai ,  Ying-Tsung Chen ,  Kei-Wei Chen

IPC: H01L21/02 ,  B08B3/12 ,  B08B1/00 ,  B08B13/00 ,  B08B3/08 ,  H01L21/67 ,  H01L21/66

Abstract: A cleaning system includes at least one cleaning module configured to receive a substrate after a chemical mechanical polishing (CMP) process and to remove contaminants on the substrate using a cleaning solution. The cleaning system further includes a cleaning solution supply system configured to supply the cleaning solution to the at least one cleaning module. The cleaning solution supply system includes at least one temperature control system. The at least one temperature control system includes a heating device configured to heat the cleaning solution, a cooling device configured to cool the cleaning solution, a temperature sensor configured to monitor a temperature of the cleaning solution, and a temperature controller configured to control the heating device and the cooling device.

公开(公告)号：US20210098308A1

公开(公告)日：2021-04-01

申请号：US17121490

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hsiung Yen ,  Ta-Chun Ma ,  Chien-Chang Su ,  Jung-Jen Chen ,  Pei-Ren Jeng ,  Chii-Horng Li ,  Kei-Wei Chen

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/165 ,  H01L29/10 ,  H01L21/02 ,  H01L21/324 ,  H01L27/092

Abstract: A device is manufactured by providing a semiconductor fin protruding from a major surface of a silicon substrate comprising silicon. A liner and a shallow trench isolation (STI) region are formed adjacent the semiconductor fin. A silicon cap is deposited over the semiconductor fin. The resulting cap consists of crystalline silicon in the portion over the semiconductor fin and consists of amorphous silicon in the portions over the liner and STI region. An HCl etch bake process is performed to remove the portions of amorphous silicon over the liner and the STI region.

公开(公告)号：US10937906B2

公开(公告)日：2021-03-02

申请号：US15974227

申请日：2018-05-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun Hsiung Tsai ,  Kei-Wei Chen

IPC: H01L29/78 ,  H01L21/306 ,  H01L21/265 ,  H01L29/66 ,  H01L29/267 ,  H01L29/165

Abstract: A semiconductor Fin FET device includes a fin structure disposed over a substrate. The fin structure includes a channel layer. The Fin FET device also includes a gate structure including a gate electrode layer and a gate dielectric layer, covering a portion of the fin structure. Side-wall insulating layers are disposed over both main sides of the gate electrode layer. The Fin FET device includes a source and a drain, each including a stressor layer disposed in a recess formed by removing the fin structure not covered by the gate structure. The stressor layer includes a first to a third stressor layer formed in this order. In the source, an interface between the first stressor layer and the channel layer is located under one of the side-wall insulating layers closer to the source or the gate electrode.

公开(公告)号：US20210036129A1

公开(公告)日：2021-02-04

申请号：US17068578

申请日：2020-10-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih Hung Chen ,  Kei-Wei Chen ,  Ying-Lang Wang

IPC: H01L29/66 ,  H01L29/40 ,  H01L21/67 ,  H01L21/321 ,  B24B37/00 ,  B24B37/10 ,  B24B7/22

Abstract: In an embodiment, a method includes: performing a self-limiting process to modify a top surface of a wafer; after the self-limiting process completes, removing the modified top surface from the wafer; and repeating the performing the self-limiting process and the removing the modified top surface from the wafer until a thickness of the wafer is decreased to a predetermined thickness.

公开(公告)号：US20200381529A1

公开(公告)日：2020-12-03

申请号：US16994865

申请日：2020-08-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hsiung Tsai ,  Kuo-Feng Yu ,  Chien-Tai Chan ,  Ziwei Fang ,  Kei-Wei Chen ,  Huai-Tei Yang

IPC: H01L29/49 ,  H01L21/225 ,  H01L29/66 ,  H01L29/78

Abstract: A gate structure, a semiconductor device, and the method of forming a semiconductor device are provided. In various embodiments, the gate structure includes a gate stack and a doped spacer overlying a sidewall of the gate stack. The gate stack contains a doped work function metal (WFM) stack and a metal gate electrode overlying the doped WFM stack.

公开(公告)号：US20200098590A1

公开(公告)日：2020-03-26

申请号：US16138806

申请日：2018-09-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Wei Hsu ,  Chi-Jen Liu ,  Kei-Wei Chen ,  Liang-Guang Chen ,  William Weilun Hong ,  Chi-hsiang Shen ,  Chia-Wei Ho ,  Yang-chun Cheng

IPC: H01L21/321 ,  H01L21/768 ,  C09G1/02

Abstract: The current disclosure describes a metal surface chemical mechanical polishing technique. A complex agent or micelle is included in the metal CMP slurry. The complex agent bonds with the oxidizer contained in the CMP slurry to form a complex, e.g., a supramolecular assembly, with an oxidizer molecule in the core of the assembly and surrounded by the complex agent molecule(s). The formed complexes have an enlarged size.

公开(公告)号：US10276715B2

公开(公告)日：2019-04-30

申请号：US15054104

申请日：2016-02-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun Hsiung Tsai ,  Chien-Tai Chan ,  Kuo-Feng Yu ,  Kei-Wei Chen

IPC: H01L29/76 ,  H01L29/78 ,  H01L29/66 ,  H01L21/306

Abstract: A fin field effect transistor (FinFET) is provided. The FinFET includes a substrate, a gate stack, and strained source and drain regions. The substrate has a semiconductor fin. The gate stack is disposed across the semiconductor fin. Moreover, the strained source and drain regions are located within recesses of the semiconductor fin beside the gate stack. Moreover, at least one of the strained source and drain regions has a top portion and a bottom portion, the bottom portion is connected to the top portion, and a bottom width of the top portion is greater than a top width of the bottom portion.