公开(公告)号：US10749011B2

公开(公告)日：2020-08-18

申请号：US16169388

申请日：2018-10-24

Applicant: International Business Machines Corporation

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Yongan Xu ,  Yi Song

IPC: H01L21/82 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L21/762 ,  H01L21/768 ,  H01L29/51 ,  H01L29/06

Abstract: Embodiments of the present invention are directed to techniques for forming a vertical field effect transistor (VFET) top spacer using an area selective cyclic deposition. In a non-limiting embodiment of the invention, a first semiconductor fin is formed over a substrate. A second semiconductor fin is formed over the substrate and adjacent to the first semiconductor fin. A dielectric isolation region is formed between the first semiconductor fin and the second semiconductor fin. A top spacer is formed between the first semiconductor fin and the second semiconductor fin by cyclically depositing dielectric layers over the dielectric isolation region. The dielectric layers are inhibited from depositing on a surface of the first semiconductor fin and on a surface of the second semiconductor fin during the cyclic deposition process.

公开(公告)号：US10658190B2

公开(公告)日：2020-05-19

申请号：US16139819

申请日：2018-09-24

Applicant: International Business Machines Corporation

Inventor： Yongan Xu ,  Ekmini Anuja De Silva ,  Su Chen Fan ,  Yann Mignot

IPC: H01L21/308 ,  G03F1/22 ,  H01L21/033

Abstract: Extreme ultraviolet (EUV) lithographic patterning methods are provided which implement directional deposition on the EUV resist mask to improve selectivity and critical dimension control during the patterning of features in multiple layers. A hard mask material is deposited on a substrate structure using directional deposition. The hard mask material forms a hard mask layer that covers patterning features of an EUV resist mask of the substrate structure. The hard mask material is etched selective to a layer underlying the EUV resist mask to remove portions of the hard mask material that were deposited on the underlying layer during the directional deposition without uncovering the patterning features of the EUV resist mask. At least one layer of the substrate structure is patterned based on the EUV resist mask and the hard mask layer.

公开(公告)号：US20200066525A1

公开(公告)日：2020-02-27

申请号：US16669835

申请日：2019-10-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hsueh-Chung Chen ,  Yongan Xu ,  Lawrence A. Clevenger ,  Yann Mignot ,  Cornelius Brown Peethala

IPC: H01L21/033 ,  G03F7/00 ,  H01L21/027 ,  G03F7/20 ,  G03F7/09 ,  H01L21/02 ,  H01L21/3105 ,  G03F7/16

Abstract: A method for fabricating a semiconductor device integrating a multiple patterning scheme includes forming a memorization layer over a plurality of mandrels and a plurality of non-mandrels, and applying an exposure scheme to the memorization layer to form at least one mandrel cut pattern and at least one non-mandrel cut pattern.

公开(公告)号：US20200058585A1

公开(公告)日：2020-02-20

申请号：US16104403

申请日：2018-08-17

Applicant: International Business Machines Corporation

Inventor： Yongan Xu ,  Junli Wang ,  Yann Mignot ,  Joe Lee

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/311 ,  H01L21/02 ,  H01L21/033 ,  H01L21/3105

Abstract: A method for manufacturing a semiconductor device includes forming a first interconnect level having a conductive metal layer formed in a first dielectric layer. In the method, a cap layer is formed on the first interconnect level, and a second interconnect level including a second dielectric layer is formed on the cap layer. The method also includes forming a third interconnect level including a third dielectric layer on the second interconnect level. An opening is formed through the second and third interconnect levels and over the conductive metal layer. Sides of the opening are lined with a spacer material, and a portion of the cap layer at a bottom of the opening is removed from a top surface of the conductive metal layer. The spacer material is removed from the opening, and a conductive material layer is deposited in the opening on the conductive metal layer.

公开(公告)号：US20190318928A1

公开(公告)日：2019-10-17

申请号：US15951266

申请日：2018-04-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Yann Mignot ,  Yongan Xu

IPC: H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/66

Abstract: A method for providing an etch mask for microelectronic processing that includes forming a material stack on a surface to be etched, wherein the material stack of at least a first material layer atop the surface to be etched for a base mandrel layer, and a second material layer atop the first material layer to provide a cap mandrel layer. If a following step, the material stack may be patterned and etched to provide double mandrel structures each including said base mandrel layer and said cap mandrel layer. A sidewall spacer is formed on sidewalls of the double mandrel structures.

公开(公告)号：US10340179B2

公开(公告)日：2019-07-02

申请号：US15703097

申请日：2017-09-13

Applicant: International Business Machines Corporation

Inventor： Cheng Chi ,  Kafai Lai ,  Chi-Chun Liu ,  Yongan Xu

IPC: H01L21/02 ,  H01L21/311 ,  H01L21/768

Abstract: A method of forming an interconnect element includes forming a trench in a dielectric material. The trench has a width equal to twice a natural pitch of a block copolymer. The block copolymer includes a first polymer and a second polymer. The method includes filling the trench with the block copolymer.

公开(公告)号：US20190187565A1

公开(公告)日：2019-06-20

申请号：US15848471

申请日：2017-12-20

Applicant: International Business Machines Corporation

Inventor： Yongan Xu ,  Jing Guo ,  Ekmini A. De Silva ,  Oleg Gluschenkov

IPC: G03F7/20 ,  H01L21/027 ,  G03F7/075 ,  G03F7/085

Abstract: An EUV lithographic structure and methods according to embodiments of the invention includes an EUV photosensitive resist layer disposed directly on an oxide hardmask layer, wherein the oxide hardmask layer is doped with dopant ions to form a doped oxide hardmask layer so as to improve adhesion between the EUV lithographic structure and the oxide hardmask. The EUV lithographic structure is free of a separate adhesion layer.

公开(公告)号：US10164060B2

公开(公告)日：2018-12-25

申请号：US15182995

申请日：2016-06-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hong He ,  Junli Wang ,  Yongan Xu ,  Yunpeng Yin

IPC: H01L29/66 ,  H01L21/762 ,  H01L29/78 ,  H01L29/06 ,  H01L21/02 ,  H01L21/311 ,  H01L21/28 ,  H01L29/08 ,  H01L29/49 ,  H01L29/40 ,  H01L29/423

Abstract: A method of forming a semiconductor device that includes forming a sacrificial gate structure on a channel portion of a fin structure, wherein the angle at the intersection of the sidewall of the sacrificial gate structure and an upper surface of the channel portion of the fin structure is obtuse. Epitaxial source and drain region structures are formed on a source region portion and a drain region portion of the fin structure. At least one dielectric material is formed on the sidewall of the sacrificial gate structure. The sacrificial gate structure may be removed to provide an opening to the channel portion of the fin structure. A function gate structure is formed in the opening. At least one angle defined by the intersection of a sidewall of the functional gate structure and an upper surface of the channel portion of the fin structure is obtuse.

公开(公告)号：US10043744B2

公开(公告)日：2018-08-07

申请号：US15800154

申请日：2017-11-01

Applicant: International Business Machines Corporation

Inventor： Victor W. C. Chan ,  Xuefeng Liu ,  Yann A. M. Mignot ,  Yongan Xu

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/28 ,  H01L21/311 ,  H01L21/768

Abstract: Techniques relate to forming a gate metal via. A gate contact has a bottom part in a first layer. A cap layer is formed on the gate contact and first layer. The gate contact is formed on top of the gate. A second layer is formed on the cap layer. The second layer and cap layer are recessed to remove a portion of the cap layer from a top part and upper sidewall parts of the gate contact. A third layer is formed on the second layer, cap layer, and gate contact. The third layer is etched through to form a gate trench over the gate contact to be around the upper sidewall parts of the gate contact. The gate trench is an opening that stops on the cap layer. Gate metal via is formed on top of the gate contact and around upper sidewall parts of the gate contact.

公开(公告)号：US10020254B1

公开(公告)日：2018-07-10

申请号：US15727956

申请日：2017-10-09

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Joe Lee ,  Yann Mignot ,  Hosadurga Shobha ,  Junli Wang ,  Yongan Xu

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/76804 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76879 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53295

Abstract: Semiconductor devices including super via structures and BEOL processes for forming the same, according to embodiments of the invention, generally include removing selected portions of a nitride cap layer intermediate interconnect levels, wherein the selected portions correspond to the regions where the super via structure is to be formed and where underlying overlay alignment markers are located.