公开(公告)号：US10140052B2

公开(公告)日：2018-11-27

申请号：US15243385

申请日：2016-08-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Derek E. Williams ,  Guy L. Guthrie ,  Sanjeev Ghai ,  William J. Starke

IPC: G06F3/06 ,  G06F12/0897 ,  G06F12/10 ,  G06F13/40

Abstract: A data processing system includes a processor core having a store-through upper level cache and a store-in lower level cache. In response to a first instruction, the processor core generates a copy-type request and transmits the copy-type request to the lower level cache, where the copy-type request specifies a source real address. In response to a second instruction, the processor core generates a paste-type request and transmits the paste-type request to the lower level cache, where the paste-type request specifies a destination real address. In response to receipt of the copy-type request, the lower level cache copies a data granule from a storage location specified by the source real address into a non-architected buffer, and in response to receipt of the paste-type request, the lower level cache writes the data granule from the non-architected buffer to a storage location specified by the destination real address.

公开(公告)号：US09766890B2

公开(公告)日：2017-09-19

申请号：US14581202

申请日：2014-12-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Lakshminarayana B. Arimilli ,  Bernard C. Drerup ,  Guy L. Guthrie ,  John D. Irish ,  William J. Starke ,  Jeffrey A. Stuecheli

IPC: G06F9/312 ,  G06F9/30 ,  G06F13/40 ,  G06F9/54

CPC classification number: G06F9/3005 ,  G06F9/3004 ,  G06F9/30047 ,  G06F9/3009 ,  G06F9/46 ,  G06F9/546 ,  G06F13/4022

Abstract: In at least some embodiments, a processor core executes a sending thread including a first push instruction and a second push instruction subsequent to the first push instruction in a program order. Each of the first and second push instructions requests that a respective message payload be pushed to a mailbox of a receiving thread. In response to executing the first and second push instructions, the processor core transmits respective first and second co-processor requests to a switch in the data processing system via an interconnect fabric of the data processing system. The processor core transmits the second co-processor request to the switch without regard to acceptance of the first co-processor request by the switch.

公开(公告)号：US09569293B2

公开(公告)日：2017-02-14

申请号：US14733631

申请日：2015-06-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Lakshminarayana B. Arimilli ,  Bernard C. Drerup ,  Bradly G. Frey ,  Guy L. Guthrie ,  John D. Irish ,  William J. Starke ,  Jeffrey A. Stuecheli

IPC: G06F3/00 ,  G06F9/44 ,  G06F9/46 ,  G06F13/00 ,  G06F9/54 ,  G06F9/30 ,  G06F13/40 ,  G06F15/167

CPC classification number: G06F9/546 ,  G06F9/30043 ,  G06F9/3009 ,  G06F9/3851 ,  G06F13/4022 ,  G06F15/167 ,  Y02D10/14 ,  Y02D10/151

Abstract: A processor core of a data processing system receives a push instruction of a sending thread that requests that a message payload identified by at least one operand of the push instruction be pushed to a mailbox of a receiving thread. In response to receiving the push instruction, the processor core executes the push instruction of the sending thread. In response to executing the push instruction, the processor core initiates transmission of the message payload to the mailbox of the receiving thread. In one embodiment, the processor core initiates transmission of the message payload by transmitting a co-processor request to a switch of the data processing system via an interconnect fabric.

公开(公告)号：US09514049B2

公开(公告)日：2016-12-06

申请号：US14523229

申请日：2014-10-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Guy L. Guthrie ,  Hien M. Le ,  William J. Starke ,  Derek E. Williams ,  Phillip G. Williams

IPC: G06F12/08 ,  G06F9/46 ,  G06F12/12

CPC classification number: G06F12/0833 ,  G06F9/467 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0897 ,  G06F12/12 ,  G06F2212/283 ,  G06F2212/62 ,  G06F2212/621

Abstract: In response to a transactional store request, the higher level cache transmits, to the lower level cache, a backup copy of an unaltered target cache line in response to a target real address hitting in the higher level cache, updates the target cache line with store data to obtain an updated target cache line, and records the target real address as belonging to a transaction footprint of the memory transaction. In response to a conflicting access to the transaction footprint prior to completion of the memory transaction, the higher level cache signals failure of the memory transaction to the processor core, invalidates the updated target cache line in the higher level cache, and causes the backup copy of the target cache line in the lower level cache to be restored as a current version of the target cache line.

公开(公告)号：US09471410B2

公开(公告)日：2016-10-18

申请号：US14037792

申请日：2013-09-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： John S. Dodson ,  Benjiman L. Goodman ,  Guy L. Guthrie ,  Eric E. Retter ,  William J. Starke ,  Jeffrey A. Stuecheli

IPC: G06F11/10 ,  G06F11/07

CPC classification number: G06F11/0751 ,  G06F11/073 ,  G06F11/1004

Abstract: In a data processing system, a memory subsystem detects whether or not at least one potentially transient condition is present that would prevent timely servicing of one or more memory access requests directed to the associated system memory. In response to detecting at least one such potentially transient condition, the memory system identifies a first read request affected by the at least one potentially transient condition. In response to identifying the read request, the memory subsystem signals to a request source to issue a second read request for the same target address by transmitting to the request source dummy data and a data error indicator.

公开(公告)号：US09231618B2

公开(公告)日：2016-01-05

申请号：US14098565

申请日：2013-12-06

Applicant: International Business Machines Corporation

Inventor： Benjiman L. Goodman ,  Harrison M. McCreary ,  Stephen J. Powell ,  William J. Starke ,  Jeffrey A. Stuecheli

IPC: G11C29/00 ,  H03M13/09 ,  G06F11/10

CPC classification number: H03M13/09 ,  G06F11/1004 ,  G06F11/1016

Abstract: A bypass mechanism allows a memory controller to transmit requested data to an interconnect before the data's error code has been decoded, e.g., a cyclical redundancy check (CRC). The tag, tag CRC, data, and data CRC are pipelined from DRAM in four frames, each having multiple clock cycles. The tag includes a bypass bit indicating whether data transmission to the interconnect should begin before CRC decoding. After receiving the tag CRC, the controller decodes it and reserves a request machine which sends a transmit request signal to inform the interconnect that data is available. Once the transmit request is granted by the interconnect, the controller can immediately start sending the data, before decoding the data CRC. So long as no error is found, the controller completes transmission of the data to the interconnect, including providing an indication that the data as transmitted is error-free.

公开(公告)号：US20150378770A1

公开(公告)日：2015-12-31

申请号：US14727245

申请日：2015-06-01

Applicant: International Business Machines Corporation

Inventor： Guy L. Guthrie ,  Naresh Nayar ,  Geraint North ,  William J. Starke ,  Albert J. Van Norstrand, JR.

IPC: G06F9/455 ,  G06F11/14

CPC classification number: G06F9/45558 ,  G06F11/14 ,  G06F11/141 ,  G06F11/1438 ,  G06F11/1458 ,  G06F11/1484 ,  G06F11/203 ,  G06F11/2035 ,  G06F11/2046 ,  G06F11/2097 ,  G06F12/08 ,  G06F12/0804 ,  G06F12/0806 ,  G06F12/0833 ,  G06F12/0855 ,  G06F12/128 ,  G06F2009/45583 ,  G06F2201/86 ,  G06F2212/151 ,  G06F2212/62 ,  G06F2212/621

Abstract: A virtual machine backup method includes utilizing a log to indicate updates to memory of a virtual machine when the updates are evicted from a cache of the virtual machine. A guard band is determined that indicates a threshold amount of free space for the log. A determination is made that the guard band will be or has been encroached upon corresponding to indicating an update in the log. A backup image of the virtual machine is updated based, at least in part, on a set of one or more entries of the log, wherein the set of entries is sufficient to comply with the guard band. The set of entries is removed from the log.

Abstract translation: 虚拟机备份方法包括当更新从虚拟机的高速缓存中逐出时利用日志指示对虚拟机的存储器的更新。 确定指示日志的可用空间的阈值量的保护带。 确定保护频段将被或被侵占对应于指示日志中的更新。 至少部分地基于日志的一个或多个条目来更新虚拟机的备份映像，其中该组条目足以符合保护带。 从日志中删除一组条目。

公开(公告)号：US09069701B2

公开(公告)日：2015-06-30

申请号：US13710927

申请日：2012-12-11

Applicant: International Business Machines Corporation

Inventor： Guy Lynn Guthrie ,  Naresh Nayar ,  Geraint North ,  William J. Starke

IPC: G06F12/12 ,  G06F12/08 ,  G06F11/14

CPC classification number: G06F12/12 ,  G06F11/14 ,  G06F11/1484 ,  G06F11/1658 ,  G06F11/202 ,  G06F11/2041 ,  G06F11/2097 ,  G06F12/0804 ,  G06F12/0806 ,  G06F2212/151

Abstract: Disclosed is a computer system (100) comprising a processor unit (110) adapted to run a virtual machine in a first operating mode; a cache (120) accessible to the processor unit, said cache including a cache controller (122); and a memory (140) accessible to the cache controller for storing an image of said virtual machine; wherein the processor unit is adapted to create a log (200) in the memory prior to running the virtual machine in said first operating mode; the cache controller is adapted to transfer a modified cache line from the cache to the memory; and write only the memory address of the transferred modified cache line in the log; and the processor unit is further adapted to update a further image of the virtual machine in a different memory location, e.g. on another computer system, by retrieving the memory addresses stored in the log, retrieve the modified cache lines from the memory addresses and update the further image with said modifications. A computer cluster including such computer systems, a method of managing such a computer cluster and a computer program product are also disclosed.

Abstract translation: 公开了一种包括适于以第一操作模式运行虚拟机的处理器单元（110）的计算机系统（100） 高速缓存（120），其可由所述处理器单元访问，所述高速缓存包括高速缓存控制器（122）; 以及高速缓存控制器可访问的存储器（140），用于存储所述虚拟机的图像; 其中所述处理器单元适于在所述第一操作模式中运行所述虚拟机之前在所述存储器中创建日志（200）; 高速缓存控制器适于将修改的高速缓存行从高速缓存传送到存储器; 并且只写日志中传输的修改高速缓存行的存储器地址; 并且所述处理器单元还适于在不同的存储器位置例如更新所述虚拟机的另一图像。 在另一计算机系统上，通过检索存储在日志中的存储器地址，从存储器地址检索修改的高速缓存行并用所述修改来更新另外的图像。 还公开了包括这种计算机系统的计算机集群，管理这种计算机集群的方法和计算机程序产品。

公开(公告)号：US09058178B2

公开(公告)日：2015-06-16

申请号：US13777729

申请日：2013-02-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Robert A. Cargnoni ,  John S. Dodson ,  Guy L. Guthrie ,  William J. Starke ,  Jeffrey A. Stuecheli

IPC: G06F11/00 ,  G06F9/38 ,  G06F13/16 ,  G06F12/08

CPC classification number: G06F9/38 ,  G06F9/3824 ,  G06F9/3842 ,  G06F9/3859 ,  G06F11/00 ,  G06F11/006 ,  G06F11/1048 ,  G06F12/0897 ,  G06F13/16

Abstract: In a data processing system, a selection is made, based at least on an access type of a memory access request, between at least a first timing and a second timing of data transmission with respect to completion of error detection processing on a target memory block of the memory access request. In response to receipt of the memory access request and selection of the first timing, data from the target memory block is transmitted to a requestor prior to completion of error detection processing on the target memory block. In response to receipt of the memory access request and selection of the second timing, data from the target memory block is transmitted to the requestor after and in response to completion of error detection processing on the target memory block.

公开(公告)号：US20150143056A1

公开(公告)日：2015-05-21

申请号：US14082199

申请日：2013-11-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Benjiman L. Goodman ,  Jody B. Joyner ,  Stephen J. Powell ,  William J. Starke ,  Jeffrey A. Stuecheli

IPC: G06F12/08 ,  G06F12/12

CPC classification number: G06F12/0828 ,  G06F12/0864 ,  G06F2212/621 ,  Y02D10/13

Abstract: A set associative cache is managed by a memory controller which places writeback instructions for modified (dirty) cache lines into a virtual write queue, determines when the number of the sets containing a modified cache line is greater than a high water mark, and elevates a priority of the writeback instructions over read operations. The controller can return the priority to normal when the number of modified sets is less than a low water mark. In an embodiment wherein the system memory device includes rank groups, the congruence classes can be mapped based on the rank groups. The number of writes pending in a rank group exceeding a different threshold can additionally be a requirement to trigger elevation of writeback priority. A dirty vector can be used to provide an indication that corresponding sets contain a modified cache line, particularly in least-recently used segments of the corresponding sets.

Abstract translation: 集合关联缓存由存储器控制器管理，存储器控制器将修改（脏）高速缓存行的回写指令放入虚拟写入队列中，确定包含修改的高速缓存行的集合的数量何时大于高水位标记，并且升高一个 回读指令优先于读取操作。 当修改集合的数量小于低水位时，控制器可以将优先级恢复为正常。 在其中系统存储器件包括等级组的实施例中，可以基于等级组映射一致等级。 超过不同阈值的等级组中挂起的写入次数还可以是触发提高回写优先级的要求。 可以使用脏向量来提供对应集合包含修改的高速缓存行的指示，特别是相应集合的最近最少使用的段。