公开(公告)号：US07723226B2

公开(公告)日：2010-05-25

申请号：US11654427

申请日：2007-01-17

申请人： Chen-Hua Yu ,  Yung-Cheng Lu ,  Pei-Ren Jeng ,  Chia-Cheng Chou ,  Keng-Chu Lin ,  Chung-Chi Ko ,  Tien-I Bao ,  Shwang-Ming Jeng

发明人： Chen-Hua Yu ,  Yung-Cheng Lu ,  Pei-Ren Jeng ,  Chia-Cheng Chou ,  Keng-Chu Lin ,  Chung-Chi Ko ,  Tien-I Bao ,  Shwang-Ming Jeng

IPC分类号： H01L21/4763

CPC分类号： H01L21/7682 ,  H01L21/76807 ,  H01L21/76835 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A bilayer porous low dielectric constant (low-k) interconnect structure and methods of fabricating the same are presented. A preferred embodiment having an effective dielectric constant of about 2.2 comprises a bottom deposited dielectric layer and a top deposited dielectric layer in direct contact with the former. The bottom layer and the top layer have same atomic compositions, but a higher dielectric constant value k. The bottom dielectric layer serves as an etch stop layer for the top dielectric layer, and the top dielectric layer can act as CMP stop layer. One embodiment of making the structure includes forming a bottom dielectric layer having a first porogen content and a top dielectric layer having a higher porogen content. A curing process leaves lower pore density in the bottom dielectric layer than that left in the top dielectric layer, which leads to higher dielectric value k in the bottom dielectric layer.

摘要翻译： 提出了双层多孔低介电常数（低k）互连结构及其制造方法。 具有约2.2的有效介电常数的优选实施例包括与前者直接接触的底部沉积的介电层和顶部沉积的介电层。 底层和顶层具有相同的原子组成，但是较高的介电常数值k。 底部介电层用作顶部介电层的蚀刻停止层，并且顶部介电层可以用作CMP停止层。 制造该结构的一个实施方案包括形成具有第一致孔剂含量的底部电介质层和具有较高致孔剂含量的顶部电介质层。 固化过程在底部电介质层中留下的孔隙密度低于顶部介电层中留下的孔密度，这导致底部介电层中较高的介电常数k。

公开(公告)号：US07446047B2

公开(公告)日：2008-11-04

申请号：US11061350

申请日：2005-02-18

申请人： Minghsing Tsai ,  Yung-Cheng Lu

发明人： Minghsing Tsai ,  Yung-Cheng Lu

IPC分类号： H01L21/311

CPC分类号： H01L21/76834 ,  H01L21/02118 ,  H01L21/0226 ,  H01L21/3127 ,  H01L21/31695 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76835

摘要： A passivated metal structure and a method of forming the metal structure is disclosed. According to one embodiment, the patterned metal structure, such as conductive lines, are formed on a substrate. The copper lines are passivated by a polymer liner between the copper lines and a low k dielectric filling the spaces between the conductive lines. The polymer liner is preferably deposited on the sidewalls of the conductive lines by electro-grafting. The polymer liner may also be used in a damascene process according to a second embodiment.

摘要翻译： 公开了钝化金属结构和形成金属结构的方法。 根据一个实施例，图案化的金属结构，例如导电线，形成在基板上。 铜线由铜线之间的聚合物衬垫和填充导电线之间的空间的低k电介质钝化。 聚合物衬垫优选通过电接枝沉积在导电线的侧壁上。 聚合物衬垫也可以用于根据第二实施例的镶嵌工艺中。

公开(公告)号：US07405481B2

公开(公告)日：2008-07-29

申请号：US11004065

申请日：2004-12-03

申请人： Keng-Chu Lin ,  Yung-Cheng Lu ,  Shwang-Ming Cheng

发明人： Keng-Chu Lin ,  Yung-Cheng Lu ,  Shwang-Ming Cheng

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L21/76832 ,  H01L21/76834 ,  H01L2924/0002 ,  H01L2924/00

摘要： In an integrated circuit chip, a conductive line is formed in a first IMD layer. The conductive line is formed of a conductive line material that tends to form an oxide when exposed to an oxygen-containing substance. A glue layer is formed on the conductive line. The glue layer is formed of a non-oxygen-containing material capable of providing an oxygen barrier over the conductive line. The glue layer has a hardness greater than that of the conductive line. The glue layer preferably has a thickness between about 15 angstroms and about 75 angstroms. The etch stop layer is formed on the glue layer. The etch stop layer has a hardness greater than that of the glue layer. A second IMD layer is formed on the etch stop layer. The etch stop layer and/or the second IMD layer may be formed with a material comprising oxygen without oxidizing the conductive line.

摘要翻译： 在集成电路芯片中，在第一IMD层中形成导线。 导电线由暴露于含氧物质时易于形成氧化物的导电线材料形成。 在导电线上形成胶层。 胶层由能够在导电线上提供氧阻隔的非含氧材料形成。 胶层的硬度大于导电线的硬度。 胶层优选地具有在约15埃至约75埃之间的厚度。 蚀刻停止层形成在胶层上。 蚀刻停止层的硬度大于胶层的硬度。 在蚀刻停止层上形成第二IMD层。 蚀刻停止层和/或第二IMD层可以由包含氧的材料形成而不氧化导电线。

公开(公告)号：US07253524B2

公开(公告)日：2007-08-07

申请号：US10797224

申请日：2004-03-10

申请人： Zhen-Cheng Wu ,  Tzu-Jen Chou ,  Weng Chang ,  Yung-Cheng Lu ,  Syun-Ming Jang ,  Mong-Song Liang

发明人： Zhen-Cheng Wu ,  Tzu-Jen Chou ,  Weng Chang ,  Yung-Cheng Lu ,  Syun-Ming Jang ,  Mong-Song Liang

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76835 ,  H01L21/76807 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor substrate has a first copper layer, on which an etch stop layer and a dielectric layer are successively formed. A second copper layer penetrates the dielectric layer and the etch stop layer to electrically connect to the first metal layer. The etch stop layer has a dielectric constant smaller than 3.5, and the dielectric layer has a dielectric constant smaller than 3.0.

摘要翻译： 半导体衬底具有第一铜层，其上依次形成有蚀刻停止层和电介质层。 第二铜层穿透电介质层和蚀刻停止层以电连接到第一金属层。 蚀刻停止层的介电常数小于3.5，电介质层的介电常数小于3.0。

公开(公告)号：US07247571B2

公开(公告)日：2007-07-24

申请号：US11226979

申请日：2005-09-15

申请人： Ying-Tsung Chen ,  Yung-Cheng Lu ,  Zhen-Cheng Wu ,  Pi-Tsung Chen

发明人： Ying-Tsung Chen ,  Yung-Cheng Lu ,  Zhen-Cheng Wu ,  Pi-Tsung Chen

IPC分类号： H01L21/311

CPC分类号： H01L21/31053 ,  H01L22/20

摘要： A method for planarizing a semiconductor structure is disclosed. A semiconductor substrate having a first area in which one or more trenches are formed in a first pattern density, and a second area in which one or more trenches are formed in a second pattern density lower than the first pattern density, is provided. A first dielectric layer is formed above the semiconductor for covering the trenches in the first and second areas. A first chemical mechanical polishing is performed on the first dielectric layer using a predetermined type of slurry for reducing a thickness thereof. The first dielectric layer is then rinsed. A second chemical mechanical polishing is performed on the first dielectric layer using the predetermined type of slurry for further removing the first dielectric layer outside the trenches, thereby reducing a step height variation between surfaces of the first and second areas.

公开(公告)号：US20070013009A1

公开(公告)日：2007-01-18

申请号：US11181915

申请日：2005-07-15

申请人： Zhen-Cheng Wu ,  Yung-Cheng Lu ,  Pi-Tsung Chen ,  Ying-Tsung Chen

发明人： Zhen-Cheng Wu ,  Yung-Cheng Lu ,  Pi-Tsung Chen ,  Ying-Tsung Chen

IPC分类号： H01L29/78 ,  H01L21/8234

CPC分类号： H01L21/823462 ,  H01L27/088 ,  Y10S438/981

摘要： A semiconductor device includes a semiconductor substrate, wherein the semiconductor substrate includes a core area for core circuits and a peripheral area for peripheral circuits. The semiconductor device includes a core oxide on the semiconductor substrate in the core area, a portion of the core oxide being nitrided, a first polysilicon pattern on the core oxide, an I/O oxide including pure oxide on the semiconductor substrate in the peripheral area, and a second polysilicon pattern on the I/O oxide.

摘要翻译： 半导体器件包括半导体衬底，其中半导体衬底包括用于核心电路的核心区域和用于外围电路的外围区域。 半导体器件在核心区域中的半导体衬底上具有核心氧化物，核心氧化物的一部分被氮化，核心氧化物上的第一多晶硅图案，在周边区域中的半导体衬底上的纯氧化物的I / O氧化物 ，以及I / O氧化物上的第二多晶硅图案。

公开(公告)号：US20050260864A1

公开(公告)日：2005-11-24

申请号：US10765361

申请日：2004-01-27

申请人： Tzu-Fang Huang ,  Yung-Cheng Lu ,  Li-Qun Xia ,  Ellie Yieh ,  Wai-Fan Yau ,  David Cheung ,  Ralf Willecke ,  Kuowei Liu ,  Ju-Hyung Lee ,  Farhad Moghadam ,  Yeming Ma

发明人： Tzu-Fang Huang ,  Yung-Cheng Lu ,  Li-Qun Xia ,  Ellie Yieh ,  Wai-Fan Yau ,  David Cheung ,  Ralf Willecke ,  Kuowei Liu ,  Ju-Hyung Lee ,  Farhad Moghadam ,  Yeming Ma

IPC分类号： C23C16/04 ,  C23C16/40 ,  H01L21/316 ,  H01L21/469 ,  H01L21/768 ,  H01L23/522

CPC分类号： H01L21/31612 ,  C23C16/045 ,  C23C16/401 ,  H01L21/02126 ,  H01L21/02208 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02304 ,  H01L21/02362 ,  H01L21/31633 ,  H01L21/76801 ,  H01L21/76808 ,  H01L21/76829 ,  H01L21/76835 ,  H01L2221/1031

摘要： A silicon oxide layer is produced by plasma enhanced decomposition of an organosilicon compound to deposit films having a carbon content of at least 1% by atomic weight. An optional carrier gas may be introduced to facilitate the deposition process at a flow rate less than or equal to the flow rate of the organosilicon compounds. An oxygen rich surface may be formed adjacent the silicon oxide layer by temporarily increasing oxidation of the organosilicon compound.

摘要翻译： 氧化硅层通过有机硅化合物的等离子体增强分解产生，以沉积碳原子量至少为1％的膜。 可以引入任选的载气，以便以小于或等于有机硅化合物的流速的流速促进沉积过程。 可以通过暂时增加有机硅化合物的氧化而在氧化硅层附近形成富氧表面。

公开(公告)号：US20050215052A1

公开(公告)日：2005-09-29

申请号：US10810970

申请日：2004-03-26

申请人： Mong-Song Liang ,  Yung-Cheng Lu ,  Huilin Chang

发明人： Mong-Song Liang ,  Yung-Cheng Lu ,  Huilin Chang

IPC分类号： H01L21/3105 ,  H01L21/44 ,  H01L21/76 ,  H01L21/768

CPC分类号： H01L21/76826 ,  H01L21/3105 ,  H01L21/76825 ,  H01L21/76828

摘要： An integrated method comprises providing a low dielectric material, applying a first treatment altering a first property of the low dielectric material, and applying a second treatment altering a second property of the treated low dielectric material and producing a lower dielectric material with better mechanical stability.

摘要翻译： 集成方法包括提供低电介质材料，施加改变低电介质材料的第一特性的第一处理，以及施加改变所处理的低电介质材料的第二特性并产生具有更好的机械稳定性的较低电介质材料的第二处理。

公开(公告)号：US06869896B2

公开(公告)日：2005-03-22

申请号：US10647959

申请日：2003-08-26

申请人： David Cheung ,  Wai-Fan Yau ,  Robert P. Mandal ,  Shin-Puu Jeng ,  Kuo-Wei Liu ,  Yung-Cheng Lu ,  Michael Barnes ,  Ralf B. Willecke ,  Farhad Moghadam ,  Tetsuya Ishikawa ,  Tze Wing Poon

发明人： David Cheung ,  Wai-Fan Yau ,  Robert P. Mandal ,  Shin-Puu Jeng ,  Kuo-Wei Liu ,  Yung-Cheng Lu ,  Michael Barnes ,  Ralf B. Willecke ,  Farhad Moghadam ,  Tetsuya Ishikawa ,  Tze Wing Poon

IPC分类号： C23C16/40 ,  H01L21/316 ,  H01L21/768 ,  H01L21/31

CPC分类号： H01L21/76835 ,  C23C16/401 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02208 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02304 ,  H01L21/02362 ,  H01L21/31612 ,  H01L21/76801 ,  H01L21/76808 ,  H01L21/7681 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L2221/1031 ,  Y10T428/24926 ,  Y10T428/31663

摘要： A method and apparatus for depositing a low dielectric constant film by reaction of an organosilicon compound and an oxidizing gas comprising carbon at a constant RF power level. Dissociation of the oxidizing gas can be increased prior to mixing with the organosilicon compound, preferably within a separate microwave chamber, to assist in controlling the carbon content of the deposited film. The oxidized organosilane or organosiloxane film has good barrier properties for use as a liner or cap layer adjacent other dielectric layers. The oxidized organosilane or organosiloxane film may also be used as an etch stop and an intermetal dielectric layer for fabricating dual damascene structures. The oxidized organosilane or organosiloxane films also provide excellent adhesion between different dielectric layers.

摘要翻译： 一种通过有机硅化合物和包含碳的氧化气体以恒定的RF功率水平的反应沉积低介电常数膜的方法和装置。 在与有机硅化合物混合之前，优选在单独的微波室内可以提高氧化气体的离解，以帮助控制沉积膜的碳含量。 氧化的有机硅烷或有机硅氧烷膜具有良好的屏障性能，用作邻近其它介电层的衬垫层或盖层。 氧化的有机硅烷或有机硅氧烷膜也可以用作蚀刻停止层和用于制造双镶嵌结构的金属间介电层。 氧化的有机硅烷或有机硅氧烷膜也在不同的介电层之间提供优异的粘附性。

公开(公告)号：US06734115B2

公开(公告)日：2004-05-11

申请号：US10229992

申请日：2002-08-27

申请人： David Cheung ,  Wai-Fan Yau ,  Robert P. Mandal ,  Shin-Puu Jeng ,  Kuo-Wei Liu ,  Yung-Cheng Lu ,  Michael Barnes ,  Ralf B. Willecke ,  Farhad Moghadam ,  Tetsuya Ishikawa ,  Tze Wing Poon

发明人： David Cheung ,  Wai-Fan Yau ,  Robert P. Mandal ,  Shin-Puu Jeng ,  Kuo-Wei Liu ,  Yung-Cheng Lu ,  Michael Barnes ,  Ralf B. Willecke ,  Farhad Moghadam ,  Tetsuya Ishikawa ,  Tze Wing Poon

IPC分类号： H01L2131

CPC分类号： H01L21/76835 ,  C23C16/401 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02208 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02304 ,  H01L21/02362 ,  H01L21/31612 ,  H01L21/76801 ,  H01L21/76808 ,  H01L21/7681 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L2221/1031 ,  Y10T428/24926 ,  Y10T428/31663

摘要： A method and apparatus for depositing a low dielectric constant film by reaction of an organosilicon compound and an oxidizing gas comprising carbon at a constant RF power level. Dissociation of the oxidizing gas can be increased prior to mixing with the organosilicon compound, preferably within a separate microwave chamber, to assist in controlling the carbon content of the deposited film. The oxidized organosilane or organosiloxane film has good barrier properties for use as a liner or cap layer adjacent other dielectric layers. The oxidized organosilane or organosiloxane film may also be used as an etch stop and an intermetal dielectric layer for fabricating dual damascene structures. The oxidized organosilane or organosiloxane films also provide excellent adhesion between different dielectric layers.