公开(公告)号：US07683438B2

公开(公告)日：2010-03-23

申请号：US12125778

申请日：2008-05-22

Applicant: Pei-Ren Jeng

Inventor： Pei-Ren Jeng

IPC: H01L27/088

CPC classification number: H01L29/7881 ,  B82Y10/00 ,  H01L21/28273 ,  H01L29/42332 ,  H01L29/66825

Abstract: A nanocrystal memory element and a method for fabricating the same are proposed. The fabricating method involves selectively oxidizing polysilicon not disposed beneath and not covered with a plurality of metal nanocrystals, and leaving intact the polysilicon disposed beneath and thereby covered with the plurality of metal nanocrystals, with a view to forming double layered silicon-metal nanocrystals by self-alignment.

Abstract translation: 提出了纳米晶体存储元件及其制造方法。 该制造方法包括选择性地氧化未设置在多个金属纳米晶体下面并且未被多个金属纳米晶体覆盖的多晶硅，并且将多晶硅置于下面并由此被多个金属纳米晶体覆盖，以便通过自身形成双层硅金属纳米晶体 -对准。

公开(公告)号：US20080217683A1

公开(公告)日：2008-09-11

申请号：US12125778

申请日：2008-05-22

Applicant: Pei-Ren Jeng

Inventor： Pei-Ren Jeng

IPC: H01L29/792 ,  H01L29/423

CPC classification number: H01L29/7881 ,  B82Y10/00 ,  H01L21/28273 ,  H01L29/42332 ,  H01L29/66825

Abstract: A nanocrystal memory element and a method for fabricating the same are proposed. The fabricating method involves selectively oxidizing polysilicon not disposed beneath and not covered with a plurality of metal nanocrystals, and leaving intact the polysilicon disposed beneath and thereby covered with the plurality of metal nanocrystals, with a view to forming double layered silicon-metal nanocrystals by self-alignment.

Abstract translation: 提出了纳米晶体存储元件及其制造方法。 该制造方法包括选择性地氧化未设置在多个金属纳米晶体下面并且未被多个金属纳米晶体覆盖的多晶硅，并且将多晶硅置于下面并由此被多个金属纳米晶体覆盖，以便通过自身形成双层硅金属纳米晶体 -对准。

公开(公告)号：US06984553B2

公开(公告)日：2006-01-10

申请号：US10385483

申请日：2003-03-12

Applicant: Pei-Ren Jeng

Inventor： Pei-Ren Jeng

IPC: H01L21/8238 ,  H01L21/331 ,  H01L21/76

CPC classification number: H01L21/76235

Abstract: In a manufacturing method for a shallow trench isolation, first, a multi-layer structure is formed over a semiconductor substrate. A first trench is formed in the multi-layer structure to define an isolation region and an active region. Sidewalls in the first trench are formed by depositing sidewall material over the multi-layer structure and surfaces of the first trench and etching the sidewall material. An isolation trench is then formed in the substrate by etching the substrate using the sidewalls and the multi-layer structure as a mask. Then the sidewalls are etched back to expose a portion of the substrate surface. Thermal oxidation is performed to oxidize the second trench, wherein the etched sidewalls and the multi-layer structure protect the substrate underneath from being oxidized. Then, the oxidized second trench is filled with a filling material and the whole structure is polished. The amount by which the sidewalls are etched back controls a bird beak that is formed in the active region.

Abstract translation: 在浅沟槽隔离的制造方法中，首先，在半导体衬底上形成多层结构。 在多层结构中形成第一沟槽以限定隔离区域和有源区域。 通过在多层结构和第一沟槽的表面上沉积侧壁材料并蚀刻侧壁材料来形成第一沟槽中的侧壁。 然后通过使用侧壁和多层结构作为掩模蚀刻衬底，在衬底中形成隔离沟槽。 然后将侧壁回蚀以露出衬底表面的一部分。 执行热氧化以氧化第二沟槽，其中蚀刻的侧壁和多层结构保护下方的衬底不被氧化。 然后，用填充材料填充氧化的第二沟槽，并且整个结构被抛光。 侧壁被回蚀的量控制在活性区域中形成的鸟嘴。

公开(公告)号：US06908814B2

公开(公告)日：2005-06-21

申请号：US10725556

申请日：2003-12-03

Applicant: Pei-Ren Jeng ,  Lin-Wu Yang

Inventor： Pei-Ren Jeng ,  Lin-Wu Yang

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/44

CPC classification number: H01L21/28273

Abstract: A selfaligned process for a flash memory comprises applying a solution with a high etch selectivity to etch the sidewall of the tungsten silicide in the gate structure of the flash memory during a clean process before forming a spacer for the gate structure. This process prevents the gate structure from degradation caused by thermal stress.

Abstract translation: 用于闪速存储器的自对准过程包括在形成用于栅极结构的间隔物之前，在清洁过程期间施加具有高蚀刻选择性的溶液来蚀刻闪存的栅极结构中的硅化钨的侧壁。 该过程防止栅极结构由热应力引起的劣化。

公开(公告)号：US06664182B2

公开(公告)日：2003-12-16

申请号：US09840994

申请日：2001-04-25

Applicant: Pei-Ren Jeng

Inventor： Pei-Ren Jeng

IPC: H01L214763

CPC classification number: H01L21/76829 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76825

Abstract: The present invention provides for an improvement of the interlayer adhesion property of the low-K layers in a dual damascene process. The method includes a shallow ion implantation process to bombard a bottom low-k layer for forming a densified layer on the bottom low-k layer. The densified layer can be a used as a substitute in the oxidation of the prior art to avoid the peeling phenomenon between the organic low-k layers.

公开(公告)号：US06559009B2

公开(公告)日：2003-05-06

申请号：US09820303

申请日：2001-03-29

Applicant: Pei-Ren Jeng

Inventor： Pei-Ren Jeng

IPC: H01L218246

CPC classification number: H01L27/105 ,  H01L27/11526 ,  H01L27/11543

Abstract: The present invention provides a method of fabricating a flash memory. The method first involves forming a gate oxide layer on a silicon substrate of a semiconductor wafer. Then, a first polysilicon layer, and a silicon nitride layer are formed, respectively, on the gate oxide layer. A lithographic process is then used to pattern a first photoresist layer for defining a memory array area and a peripheral region. The first photoresist layer is then used to etch the silicon nitride layer down to the surface of the silicon substrate to form a wide gap at the boundary between the memory array area and the peripheral region, and a plurality of gaps in the memory array area. An HDP oxide layer is then deposited, followed by coating of a photoresist (PR) on the wafer to achieve cell planarization. Thereafter, an oxide etch back process is performed followed by stripping of both the PR coating and the silicon nitride layer. Finally, a floating gate and a control gate are formed, respectively.

公开(公告)号：US06472271B1

公开(公告)日：2002-10-29

申请号：US09863303

申请日：2001-05-24

Applicant: Pei-Ren Jeng

Inventor： Pei-Ren Jeng

IPC: H01L21336

CPC classification number: H01L27/11526 ,  H01L21/31056 ,  H01L27/105 ,  H01L27/11531

Abstract: The present invention discloses a planarization method of memory unit of a flash memory, wherein a patterned polysilicon layer and a silicon nitride layer are formed in turn on a semiconductor substrate. A silicon dioxide layer is then deposited by the HDPCVD technique. Next, a silicon nitride layer is deposited. Finally, the silicon nitride layer and the silicon dioxide layer thereon are simultaneously removed using hot phosphoric acid. Because the CMP technique is not used in the present invention, the problem of micro scratches will not arise. Therefore, the present invention can assure the requirement of high planarity of memory unit of the flash memory, simplify the process flow, increase the tolerance of the etching mask, and effectively enhance the function of memory unit.

Abstract translation: 本发明公开了一种闪速存储器存储单元的平面化方法，其中在半导体衬底上依次形成图案化多晶硅层和氮化硅层。 然后通过HDPCVD技术沉积二氧化硅层。 接下来，沉积氮化硅层。 最后，使用热磷酸同时除去其上的氮化硅层和二氧化硅层。 由于在本发明中不使用CMP技术，所以不会产生微小划伤的问题。 因此，本发明可以确保对闪速存储器的高平坦度的要求，简化工艺流程，增加蚀刻掩模的公差，并有效地增强存储单元的功能。

公开(公告)号：US06407454B1

公开(公告)日：2002-06-18

申请号：US09712727

申请日：2000-11-14

Applicant: Ping-Yi Chang ,  Pei-Ren Jeng ,  Chi-Tung Huang

Inventor： Ping-Yi Chang ,  Pei-Ren Jeng ,  Chi-Tung Huang

IPC: H01L2328

CPC classification number: H01L21/02131 ,  C23C16/401 ,  H01L21/02274 ,  H01L21/02362 ,  H01L21/31629 ,  H01L21/76819 ,  H01L21/76837 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for manufacturing dielectric layers between metal parts by forming fluorine silicate glass by high density plasma deposition using radio frequency power of low bias voltage. The method includes filling in a gap with fluorine silicate glass by high density plasma deposition with slower rate of deposition and radio frequency power of high bias voltage, and then using fluorine silicate glass deposited with fast rate of deposition and radio frequency power of no or low bias voltage as a sacrificial layer, and being made plane by a chemical-mechanic polishing CMP.

Abstract translation: 一种通过使用低偏压的射频功率通过高密度等离子体沉积形成氟硅酸盐玻璃来在金属部件之间制造电介质层的方法。 该方法包括以较低的沉积速率和较高的偏置电压的射频功率通过高密度等离子体沉积与氟硅酸盐玻璃填充间隙，然后使用沉积速度较快的无硅或低频的氟硅酸盐玻璃 偏置电压作为牺牲层，并通过化学机械抛光CMP制成平面。

公开(公告)号：US06403424B1

公开(公告)日：2002-06-11

申请号：US09967955

申请日：2001-10-02

Applicant: Chung-Yeh Lee ,  Pei-Ren Jeng ,  Henry Chung

Inventor： Chung-Yeh Lee ,  Pei-Ren Jeng ,  Henry Chung

IPC: H01L21336

CPC classification number: H01L21/76897 ,  H01L21/76807 ,  H01L27/112 ,  H01L27/1126

Abstract: A method for forming a self-aligned mask read only memory by dual damascene trenches is disclosed. In the method, a thickness difference is formed between the gate area and periphery to be formed with a dual damascene trench so as to be formed with a condition of self-alignment of read only memory code. Thus, the manufacturing range in the lithography is enlarged, and an ion implantation process with self-aligned ability complete. Therefore, self-aligned read only memory codes and metal word lines are formed. The defect of disalignment in the read only memory code is resolved and the difficulty in the manufacturing process is reduced.

Abstract translation: 公开了一种通过双镶嵌沟槽形成自对准掩模只读存储器的方法。 在该方法中，在栅极区域和周边之间形成厚度差以形成双镶嵌沟槽，以形成具有只读存储器代码的自对准的条件。 因此，光刻中的制造范围扩大，具有自对准能力的离子注入工艺完成。 因此，形成自对准的只读存储器代码和金属字线。 仅读存储器代码中的不对齐的缺陷被解决，并且制造过程中的难度降低。

公开(公告)号：US06391718B1

公开(公告)日：2002-05-21

申请号：US09788705

申请日：2001-02-20

Applicant: Pei-Ren Jeng

Inventor： Pei-Ren Jeng

IPC: H01L21336

CPC classification number: H01L27/11526 ,  H01L21/31056 ,  H01L27/105 ,  H01L27/11531

Abstract: A method to planarize a flash memory device, wherein the method is applied on a substrate having a polysilicon layer and a cap layer sequentially formed thereon. Thereafter, the cap layer and the polysilicon layer are patterned to form the peripheral circuit region and the memory cell region. A dielectric layer is then formed on the substrate, covering the cap layer. A portion of the dielectric layer is further removed to expose a part of the cap layer, such that the dielectric layer above the cap layer and the dielectric layer on both sides of the cap layer become separated. A portion of the dielectric layer in the peripheral circuit region is then removed, followed by forming a photoresist layer on the substrate such that a portion of the dielectric layer in the peripheral circuit region and in the memory cell region is exposed. The dielectric layer exposed by the photoresist layer is then removed, followed by removing the photoresist layer. The cap layer is subsequently removed to complete the planazation of the flash memory device.

Abstract translation: 一种平面化闪速存储器件的方法，其中所述方法被施加在其上顺序地形成有多晶硅层和盖层的衬底上。 此后，盖层和多晶硅层被图案化以形成外围电路区域和存储单元区域。 然后在衬底上形成介电层，覆盖覆盖层。 进一步去除电介质层的一部分以露出盖层的一部分，使得覆盖层上方的电介质层和盖层两侧的电介质层变得分离。 然后去除外围电路区域中的介电层的一部分，然后在基板上形成光致抗蚀剂层，使得外围电路区域和存储单元区域中的介电层的一部分露出。 然后去除由光致抗蚀剂层暴露的电介质层，然后除去光致抗蚀剂层。 随后去除盖层以完成闪存装置的平面化。