公开(公告)号：US06403424B1

公开(公告)日：2002-06-11

申请号：US09967955

申请日：2001-10-02

Applicant: Chung-Yeh Lee ,  Pei-Ren Jeng ,  Henry Chung

Inventor： Chung-Yeh Lee ,  Pei-Ren Jeng ,  Henry Chung

IPC: H01L21336

CPC classification number: H01L21/76897 ,  H01L21/76807 ,  H01L27/112 ,  H01L27/1126

Abstract: A method for forming a self-aligned mask read only memory by dual damascene trenches is disclosed. In the method, a thickness difference is formed between the gate area and periphery to be formed with a dual damascene trench so as to be formed with a condition of self-alignment of read only memory code. Thus, the manufacturing range in the lithography is enlarged, and an ion implantation process with self-aligned ability complete. Therefore, self-aligned read only memory codes and metal word lines are formed. The defect of disalignment in the read only memory code is resolved and the difficulty in the manufacturing process is reduced.

Abstract translation: 公开了一种通过双镶嵌沟槽形成自对准掩模只读存储器的方法。 在该方法中，在栅极区域和周边之间形成厚度差以形成双镶嵌沟槽，以形成具有只读存储器代码的自对准的条件。 因此，光刻中的制造范围扩大，具有自对准能力的离子注入工艺完成。 因此，形成自对准的只读存储器代码和金属字线。 仅读存储器代码中的不对齐的缺陷被解决，并且制造过程中的难度降低。

公开(公告)号：US20120280317A1

公开(公告)日：2012-11-08

申请号：US13169052

申请日：2011-06-27

Applicant: Chung-Yeh Lee ,  Pei-Hsun Wu ,  Shiang-Wen Huang

Inventor： Chung-Yeh Lee ,  Pei-Hsun Wu ,  Shiang-Wen Huang

IPC: H01L29/772 ,  H01L29/06

CPC classification number: H01L29/7817 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7826

Abstract: A reduced surface field (RESURF) structure and a lateral diffused metal oxide semiconductor (LDMOS) device including the same are provided. The RESURF structure includes a substrate of a first conductivity type, a deep well region of a second conductivity type, an isolation structure, at least one trench insulating structure, and at least one doped region of the first conductivity type. The deep well region is disposed in the substrate. The isolation structure is disposed on the substrate. The trench insulating structure is disposed in the deep well region below the isolation structure. The doped region is disposed in the deep well region and surrounds a sidewall and a bottom of the trench insulating structure.

Abstract translation: 提供减小的表面场（RESURF）结构和包括其的横向扩散金属氧化物半导体（LDMOS）器件。 RESURF结构包括第一导电类型的衬底，第二导电类型的深阱区，隔离结构，至少一个沟槽绝缘结构和至少一个第一导电类型的掺杂区。 深井区域设置在基板中。 隔离结构设置在基板上。 沟槽绝缘结构设置在隔离结构下方的深井区域中。 掺杂区域设置在深阱区域中并且包围沟槽绝缘结构的侧壁和底部。

公开(公告)号：US07538396B2

公开(公告)日：2009-05-26

申请号：US11624693

申请日：2007-01-19

Applicant: Shih-Kuei Ma ,  Chung-Yeh Lee ,  Chun-Ying Yeh ,  Wei-Ting Kuo

Inventor： Shih-Kuei Ma ,  Chung-Yeh Lee ,  Chun-Ying Yeh ,  Wei-Ting Kuo

IPC: H01L27/092

CPC classification number: H01L27/0921 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0928 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/7835

Abstract: A semiconductor device includes a substrate, an epitaxial layer, a sinker, an active device, a first buried layer, and a second buried layer. The substrate has a first type conductivity. The epitaxial layer has a second type conductivity, and is located on the substrate. The sinker has the second type conductivity, and is located in the epitaxial layer. The sinker extends from the substrate to an upper surface of the epitaxial layer, and partitions a region off from the epitaxial layer. The active device is located within the region. The first buried layer has the first type conductivity, and is located between the region and the substrate. The second buried layer has the second type conductivity, and is located between the first buried layer and the substrate. The second buried layer connects with the sinker. Because of the above-mentioned configuration, latch-up can be prevented.

Abstract translation: 半导体器件包括衬底，外延层，沉降片，有源器件，第一掩埋层和第二掩埋层。 衬底具有第一类型的导电性。 外延层具有第二类型的导电性，并且位于基板上。 沉降片具有第二类型的导电性，并且位于外延层中。 沉降片从衬底延伸到外延层的上表面，并且将区域从外延层分隔开。 有源设备位于该区域内。 第一掩埋层具有第一类型的导电性，并且位于区域和衬底之间。 第二掩埋层具有第二类型的导电性，并且位于第一埋层和衬底之间。 第二埋层与沉降片连接。 由于上述结构，可以防止闩锁。

公开(公告)号：US07411271B1

公开(公告)日：2008-08-12

申请号：US11624694

申请日：2007-01-19

Applicant: Shih-Kuei Ma ,  Chung-Yeh Lee ,  Chun-Ying Yeh ,  Shin-Cheng Lin

Inventor： Shih-Kuei Ma ,  Chung-Yeh Lee ,  Chun-Ying Yeh ,  Shin-Cheng Lin

IPC: H01L29/00

CPC classification number: H01L27/092 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0921

Abstract: A complementary metal-oxide-semiconductor field effect transistor (CMOSFET) is provided. The CMOSFET includes a substrate of a first conductivity type, a first epitaxial layer, a well, a second epitaxial layer of a second conductivity type, a first sinker, a second sinker, a first buried layer and a second buried layer. The first and the second epitaxial layer are sequentially disposed on the substrate. The first sinker and the first buried layer separate a first region from the second epitaxial layer. The second sinker and the second buried layer separate a second region from the second epitaxial layer. The well is disposed in the first region. A first transistor is disposed in the well. A second transistor is disposed in the second region. A deep trench isolation is disposed between the first and the second region and extends from the substrate to the upper surface of the second epitaxial layer.

Abstract translation: 提供了互补金属氧化物半导体场效应晶体管（CMOSFET）。 CMOSFET包括第一导电类型的衬底，第一外延层，阱，第二导电类型的第二外延层，第一沉陷片，第二沉陷片，第一掩埋层和第二掩埋层。 第一和第二外延层依次设置在基板上。 第一沉降片和第一掩埋层将第一区域与第二外延层分开。 第二沉降片和第二掩埋层将第二区域与第二外延层分开。 井位于第一区域。 第一晶体管设置在阱中。 第二晶体管设置在第二区域中。 深沟槽隔离设置在第一和第二区域之间并且从衬底延伸到第二外延层的上表面。

公开(公告)号：US08853738B2

公开(公告)日：2014-10-07

申请号：US13169058

申请日：2011-06-27

Applicant: Chung-Yeh Lee ,  Pei-Hsun Wu ,  Shiang-Wen Huang

Inventor： Chung-Yeh Lee ,  Pei-Hsun Wu ,  Shiang-Wen Huang

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L29/7816 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/42368

Abstract: A power LDMOS device including a substrate, source and drain regions, gates and trench insulating structures is provided. The substrate has a finger tip area, a finger body area and a palm area. The source regions are in the substrate in the finger body area and further extend to the finger tip area. The neighboring source regions in the finger tip area are connected. The outmost two source regions further extend to the palm area and are connected. The drain regions are in the substrate in the finger body area and further extend to the palm area. The neighboring drain regions in the palm area are connected. The source and drain regions are disposed alternately. A gate is disposed between the neighboring source and drain regions. The trench insulating structures are in the substrate in the palm area and respectively surround ends of the drain regions.

Abstract translation: 提供了包括衬底，源极和漏极区域，栅极和沟槽绝缘结构的功率LDMOS器件。 基底具有指尖区域，手指体区域和手掌区域。 源区域在手指主体区域中的基底中，并且进一步延伸到指尖区域。 指尖区域中的相邻源区域被连接。 最远的两个源区域进一步延伸到手掌区域并被连接。 漏极区域位于手指主体区域中的基板中，并且进一步延伸到手掌区域。 手掌区域中的相邻漏极区域被连接。 源区和漏区交替布置。 栅极设置在相邻的源区和漏区之间。 沟槽绝缘结构位于手掌区域中的基板中，并且分别围绕漏极区域的端部。

公开(公告)号：US08785969B2

公开(公告)日：2014-07-22

申请号：US13169052

申请日：2011-06-27

Applicant: Chung-Yeh Lee ,  Pei-Hsun Wu ,  Shiang-Wen Huang

Inventor： Chung-Yeh Lee ,  Pei-Hsun Wu ,  Shiang-Wen Huang

IPC: H01L29/78

CPC classification number: H01L29/7817 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7826

Abstract: A reduced surface field (RESURF) structure and a lateral diffused metal oxide semiconductor (LDMOS) device including the same are provided. The RESURF structure includes a substrate of a first conductivity type, a deep well region of a second conductivity type, an isolation structure, at least one trench insulating structure, and at least one doped region of the first conductivity type. The deep well region is disposed in the substrate. The isolation structure is disposed on the substrate. The trench insulating structure is disposed in the deep well region below the isolation structure. The doped region is disposed in the deep well region and surrounds a sidewall and a bottom of the trench insulating structure.

Abstract translation: 提供减小的表面场（RESURF）结构和包括其的横向扩散金属氧化物半导体（LDMOS）器件。 RESURF结构包括第一导电类型的衬底，第二导电类型的深阱区，隔离结构，至少一个沟槽绝缘结构和至少一个第一导电类型的掺杂区。 深井区域设置在基板中。 隔离结构设置在基板上。 沟槽绝缘结构设置在隔离结构下方的深井区域中。 掺杂区域设置在深阱区域中并且包围沟槽绝缘结构的侧壁和底部。

公开(公告)号：US06503832B2

公开(公告)日：2003-01-07

申请号：US09781429

申请日：2001-02-13

Applicant: Hung Wei Liu ,  Chi Tung Huang ,  Chung Yeh Lee ,  Chien Chia Lin

Inventor： Hung Wei Liu ,  Chi Tung Huang ,  Chung Yeh Lee ,  Chien Chia Lin

IPC: H01L2144

CPC classification number: H01L21/67017 ,  C23C16/4402 ,  Y10S438/905

Abstract: The present invention proposes an application of controlling gas valves to reduce particles from the CVD process. First, the actions of opening and closing a gas valve are added to let particles possibly adhering on the gas valve fall during the idle period between the CVD processes of a wafer and the next wafer. Next, an inert gas is led in to purge the gas valve and the reaction chamber. Finally, a gas-extracting means is used to extract the gas out. The actions of opening and closing the gas valve only take a few seconds so that the time of the next wafer entering the reaction chamber to perform the CVD process will not be influenced. The present invention has the advantage of increasing the yield of wafer while the production is not influenced and the original fabrication equipments need not be changed.

公开(公告)号：US20120261752A1

公开(公告)日：2012-10-18

申请号：US13169058

申请日：2011-06-27

Applicant: Chung-Yeh Lee ,  Pei-Hsun Wu ,  Shiang-Wen Huang

Inventor： Chung-Yeh Lee ,  Pei-Hsun Wu ,  Shiang-Wen Huang

IPC: H01L29/78

CPC classification number: H01L29/7816 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/42368

Abstract: A power LDMOS device including a substrate, source and drain regions, gates and trench insulating structures is provided. The substrate has a finger tip area, a finger body area and a palm area. The source regions are in the substrate in the finger body area and further extend to the finger tip area. The neighboring source regions in the finger tip area are connected. The outmost two source regions further extend to the palm area and are connected. The drain regions are in the substrate in the finger body area and further extend to the palm area. The neighboring drain regions in the palm area are connected. The source and drain regions are disposed alternately. A gate is disposed between the neighboring source and drain regions. The trench insulating structures are in the substrate in the palm area and respectively surround ends of the drain regions.

Abstract translation: 提供了包括衬底，源极和漏极区域，栅极和沟槽绝缘结构的功率LDMOS器件。 基底具有指尖区域，手指体区域和手掌区域。 源区域在手指主体区域中的基底中，并且进一步延伸到指尖区域。 指尖区域中的相邻源区域被连接。 最远的两个源区域进一步延伸到手掌区域并被连接。 漏极区域位于手指主体区域中的基板中，并且进一步延伸到手掌区域。 手掌区域中的相邻漏极区域被连接。 源区和漏区交替布置。 栅极设置在相邻的源区和漏区之间。 沟槽绝缘结构位于手掌区域中的基板中，并且分别围绕漏极区域的端部。

公开(公告)号：US07514754B2

公开(公告)日：2009-04-07

申请号：US11624698

申请日：2007-01-19

Applicant: Shih-Kuei Ma ,  Chung-Yeh Lee ,  Chun-Ying Yeh ,  Ker-Hsiao Huo

Inventor： Shih-Kuei Ma ,  Chung-Yeh Lee ,  Chun-Ying Yeh ,  Ker-Hsiao Huo

IPC: H01L27/092

CPC classification number: H01L21/823892 ,  H01L27/0922

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a first epitaxial layer, a first sinker, a first buried layer, a second epitaxial layer, a second sinker and a second buried layer. The first and second epitaxial layers are disposed sequentially on the substrate. The first sinker and the first buried layer define a first area from the first and the second epitaxial layers. The second sinker and the second buried layer define a second area from the second epitaxial layer in the first area. An active device is disposed in the second area. The first buried layer is disposed between the first area and the substrate, and is connected to the first sinker. The second buried layer is disposed between the second area and the first epitaxial layer, and is connected to the second sinker.

Abstract translation: 提供半导体器件。 半导体器件包括衬底，第一外延层，第一沉降片，第一掩埋层，第二外延层，第二沉没片和第二掩埋层。 第一外延层和第二外延层依次设置在基板上。 第一沉降片和第一掩埋层限定了第一和第二外延层的第一区域。 第二沉降片和第二掩埋层在第一区域中限定了第二外延层的第二区域。 有源装置设置在第二区域中。 第一掩埋层设置在第一区域和衬底之间，并且连接到第一沉降片。 第二掩埋层设置在第二区域和第一外延层之间，并且连接到第二沉陷片。

公开(公告)号：US20080173951A1

公开(公告)日：2008-07-24

申请号：US11624698

申请日：2007-01-19

Applicant: Shih-Kuei Ma ,  Chung-Yeh Lee ,  Chun-Ying Yeh ,  Ker-Hsiao Huo

Inventor： Shih-Kuei Ma ,  Chung-Yeh Lee ,  Chun-Ying Yeh ,  Ker-Hsiao Huo

IPC: H01L27/092

CPC classification number: H01L21/823892 ,  H01L27/0922

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a first epitaxial layer, a first sinker, a first buried layer, a second epitaxial layer, a second sinker and a second buried layer. The first and second epitaxial layers are disposed sequentially on the substrate. The first sinker and the first buried layer define a first area from the first and the second epitaxial layers. The second sinker and the second buried layer define a second area from the second epitaxial layer in the first area. An active device is disposed in the second area. The first buried layer is disposed between the first area and the substrate, and is connected to the first sinker. The second buried layer is disposed between the second area and the first epitaxial layer, and is connected to the second sinker.

Abstract translation: 提供半导体器件。 半导体器件包括衬底，第一外延层，第一沉降片，第一掩埋层，第二外延层，第二沉没片和第二掩埋层。 第一外延层和第二外延层依次设置在基板上。 第一沉降片和第一掩埋层限定了第一和第二外延层的第一区域。 第二沉降片和第二掩埋层在第一区域中限定了第二外延层的第二区域。 有源装置设置在第二区域中。 第一掩埋层设置在第一区域和衬底之间，并且连接到第一沉降片。 第二掩埋层设置在第二区域和第一外延层之间，并且连接到第二沉陷片。