公开(公告)号：US06589854B2

公开(公告)日：2003-07-08

申请号：US09974580

申请日：2001-10-09

Applicant: Wan-Yi Liu ,  Ping-Yi Chang

Inventor： Wan-Yi Liu ,  Ping-Yi Chang

IPC: H01L2176

CPC classification number: H01L21/76235

Abstract: A method of forming a shallow trench isolation structure. A pad oxide layer and a mask layer are sequentially formed over a substrate. A portion of the pad oxide layer, mask layer and substrate are removed to form a trench in the substrate. A first stage high-density plasma chemical vapor deposition having a high etching/deposition ratio is conducted to form a layer of insulation material over the substrate. A second stage high-density plasma chemical vapor deposition having a lower etching/deposition rate is conducted to form a second layer of insulation material over the substrate and completely fills the trench. Insulating material outside the trench region is removed. Finally, the mask layer and the pad oxide layer are sequentially removed to form a complete STI structure.

公开(公告)号：US06407454B1

公开(公告)日：2002-06-18

申请号：US09712727

申请日：2000-11-14

Applicant: Ping-Yi Chang ,  Pei-Ren Jeng ,  Chi-Tung Huang

Inventor： Ping-Yi Chang ,  Pei-Ren Jeng ,  Chi-Tung Huang

IPC: H01L2328

CPC classification number: H01L21/02131 ,  C23C16/401 ,  H01L21/02274 ,  H01L21/02362 ,  H01L21/31629 ,  H01L21/76819 ,  H01L21/76837 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for manufacturing dielectric layers between metal parts by forming fluorine silicate glass by high density plasma deposition using radio frequency power of low bias voltage. The method includes filling in a gap with fluorine silicate glass by high density plasma deposition with slower rate of deposition and radio frequency power of high bias voltage, and then using fluorine silicate glass deposited with fast rate of deposition and radio frequency power of no or low bias voltage as a sacrificial layer, and being made plane by a chemical-mechanic polishing CMP.

Abstract translation: 一种通过使用低偏压的射频功率通过高密度等离子体沉积形成氟硅酸盐玻璃来在金属部件之间制造电介质层的方法。 该方法包括以较低的沉积速率和较高的偏置电压的射频功率通过高密度等离子体沉积与氟硅酸盐玻璃填充间隙，然后使用沉积速度较快的无硅或低频的氟硅酸盐玻璃 偏置电压作为牺牲层，并通过化学机械抛光CMP制成平面。

公开(公告)号：US06849504B2

公开(公告)日：2005-02-01

申请号：US10064266

申请日：2002-06-27

Applicant: Ping-Yi Chang ,  Pei-Ren Jeng

Inventor： Ping-Yi Chang ,  Pei-Ren Jeng

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L27/11521 ,  H01L27/115 ,  Y10S438/931

Abstract: A method for fabricating a flash memory is described. A stacked gate structure and a source/drain are formed on a substrate. An inter-layer dielectrics and a plurality of inter-metal dielectric layers are then formed over the substrate, wherein at least one layer among the inter-layer dielectrics and the inter-metal dielectric layers has a silicon carbide layer formed thereon. The silicon carbide layer is formed to protect the memory device from an UV irradiation, so as to prevent data errors occurring in the memory device.

Abstract translation: 描述了一种用于制造闪速存储器的方法。 堆叠的栅极结构和源极/漏极形成在衬底上。 然后在衬底上形成层间电介质和多个金属间电介质层，其中层间电介质和金属间电介质层中的至少一层具有形成在其上的碳化硅层。 形成碳化硅层以保护存储器件免受UV照射，以防止在存储器件中发生数据错误。

公开(公告)号：US06706596B2

公开(公告)日：2004-03-16

申请号：US10209855

申请日：2002-08-02

Applicant: Ping-Yi Chang ,  Wan-Yi Liu ,  Shu-Li Wu

Inventor： Ping-Yi Chang ,  Wan-Yi Liu ,  Shu-Li Wu

IPC: H01L218247

CPC classification number: H01L27/115 ,  H01L27/11521

Abstract: The present invention provides a method for forming a flash memory cell and comprises following steps. First, a substrate is provided. Then, a gate dielectric layer, a first polysilicon layer and a hard mask layer are sequentially formed on the substrate. Next, a portion of the hard mask layer, the polysilicon layer, and the gate dielectric layer are removed to form a plurality of holes to expose the substrate. Following, a dielectric layer is formed in those holes by a HDPCVD process. Last, the hard mask layer on the first polysilicon layer is removed by the HDPCVD process. Further, a second polysilicon layer could be conformally formed on the first polysilicon layer and the isolation dielectric.

Abstract translation: 本发明提供一种形成闪存单元的方法，包括以下步骤。 首先，提供基板。 然后，在衬底上依次形成栅介电层，第一多晶硅层和硬掩模层。 接下来，去除硬掩模层，多晶硅层和栅极电介质层的一部分以形成多个孔以露出衬底。 接下来，通过HDPCVD工艺在这些孔中形成介电层。 最后，通过HDPCVD工艺去除第一多晶硅层上的硬掩模层。 此外，第二多晶硅层可以共形地形成在第一多晶硅层和隔离电介质上。

公开(公告)号：US06336841B1

公开(公告)日：2002-01-08

申请号：US09820304

申请日：2001-03-29

Applicant: Ping-Yi Chang

Inventor： Ping-Yi Chang

IPC: B24B4900

CPC classification number: B24B37/013 ,  B24B37/042 ,  B24B49/04 ,  B24B49/12

Abstract: The present invention provides an infrared spectroscopic method of removing a first layer from a semiconductor wafer without overpolishing the underlying second layer. The first layer and the second layer of the semiconductor wafer is subjected to infrared (IR) spectroscopy and an absorbance curve is produced, whereby each layer absorbs IR light at different wavenumbers to produce different absorbance peaks. Once the CMP process is performed, a change in the IR absorptivity and thus the absorbance peak of each layer is detected. The endpoint of the CMP process is determined at a point when significant change in the IR absorptivity of the first layer is no longer detected and change in the IR absorptivity of the second layer occurs.

Abstract translation: 本发明提供一种从半导体晶片去除第一层而不过度抛光底层第二层的红外光谱方法。 对半导体晶片的第一层和第二层进行红外（IR）光谱分析，并产生吸光度曲线，由此各层吸收不同波数的红外光，产生不同的吸收峰。 一旦执行CMP处理，就检测到IR吸收率的改变，从而检测每个层的吸收峰。 在不再检测第一层的IR吸收率的显着变化并且发生第二层的IR吸收率的变化的时刻确定CMP工艺的终点。

公开(公告)号：US20080023084A1

公开(公告)日：2008-01-31

申请号：US11692567

申请日：2007-03-28

Applicant: Ping-Yi Chang ,  Xiao-Ping Zhang

Inventor： Ping-Yi Chang ,  Xiao-Ping Zhang

IPC: F17D1/00

CPC classification number: F17D1/086 ,  Y10T137/87185

Abstract: The present invention discloses a piping design for a high density plasma process chamber, wherein an extra pipe is added to between a process chamber and a mass flow controller, and the extra pipe together with a pump is used to drain out the gas, which cannot be monitored by the mass flow controller and survives in a gas injection pipe, lest the remaining gas pollute the deposited film or react with the process gas to induce an explosion in the succeeding deposition process.

Abstract translation: 本发明公开了一种用于高密度等离子体处理室的管道设计，其中在处理室和质量流量控制器之间添加额外的管道，并且使用额外的管道与泵一起排出不能 由质量流量控制器监控并在气体注入管道中存活，以免残留的气体污染沉积的膜或与处理气体反应，以在随后的沉积过程中引起爆炸。

公开(公告)号：US06458660B1

公开(公告)日：2002-10-01

申请号：US09986933

申请日：2001-11-13

Applicant: Ping-Yi Chang ,  Wan-Yi Liu

Inventor： Ping-Yi Chang ,  Wan-Yi Liu

IPC: H01L21336

CPC classification number: H01L27/11526 ,  H01L27/115 ,  H01L27/11531

Abstract: A method of forming memory cell having buried diffusion oxide is disclosed. The method comprises the steps of providing a substrate having a tunnel oxide layer and a first conductive layer thereon, forming trenches into said tunnel oxide layer and said first conductive layer to expose said substrate, filling said trenches with a dielectric material to a predetermined thickness, removing a portion of said first conductive layer to form a surface lower than said predetermined thickness; and forming a second conductive layer over said dielectric material and said first conductive layer.

Abstract translation: 公开了一种形成具有掩埋扩散氧化物的存储单元的方法。 该方法包括以下步骤：在其上提供具有隧道氧化物层和第一导电层的衬底，在所述隧道氧化物层和所述第一导电层中形成沟槽以暴露所述衬底，用介电材料将所述沟槽填充到预定厚度， 去除所述第一导电层的一部分以形成低于所述预定厚度的表面; 以及在所述介电材料和所述第一导电层上形成第二导电层。