公开(公告)号：US20110256694A1

公开(公告)日：2011-10-20

申请号：US13157162

申请日：2011-06-09

Applicant: David H. Wells

Inventor： David H. Wells

IPC: H01L21/20

CPC classification number: H01L21/764 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/0265 ,  H01L21/2015

Abstract: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.

Abstract translation: 一些实施例包括在半导体结构内形成空隙的方法。 在一些实施例中，空隙可以用作用于分配冷却剂的微结构，用于引导电磁辐射，或用于材料的分离和/或表征。 一些实施例包括其中具有对应于空隙，导管，绝缘结构，半导体结构或导电结构的微结构的结构。

公开(公告)号：US20110210400A1

公开(公告)日：2011-09-01

申请号：US13096953

申请日：2011-04-28

Applicant: David H. Wells ,  Eric R. Blomiley

Inventor： David H. Wells ,  Eric R. Blomiley

IPC: H01L27/088 ,  H01L27/02

CPC classification number: H01L29/1083 ,  H01L21/3221 ,  H01L27/108 ,  H01L27/10873 ,  H01L27/11 ,  H01L29/7833 ,  H01L29/7849 ,  H01L29/78648 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments include formation of at least one cavity in a first semiconductor material, followed by epitaxially growing a second semiconductor material over the first semiconductor material and bridging across the at least one cavity. The cavity may be left open, or material may be provided within the cavity. The material provided within the cavity may be suitable for forming, for example, one or more of electromagnetic radiation interaction components, transistor gates, insulative structures, and coolant structures. Some embodiments include one or more of transistor devices, electromagnetic radiation interaction components, transistor devices, coolant structures, insulative structures and gas reservoirs.

Abstract translation: 一些实施例包括在第一半导体材料中形成至少一个空腔，随后在第一半导体材料上外延生长第二半导体材料并桥接穿过至少一个空腔。 空腔可以保持打开，或者可以在空腔内提供材料。 设置在空腔内的材料可适用于形成例如电磁辐射相互作用部件，晶体管栅极，绝缘结构和冷却剂结构中的一个或多个。 一些实施例包括晶体管器件，电磁辐射相互作用元件，晶体管器件，冷却剂结构，绝缘结构和气体储存器中的一个或多个。

公开(公告)号：US08004055B2

公开(公告)日：2011-08-23

申请号：US11724649

申请日：2007-03-14

Applicant: David H. Wells

Inventor： David H. Wells

IPC: H01L29/78

CPC classification number: H01L21/764 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/0265 ,  H01L21/2015

Abstract: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.

Abstract translation: 一些实施例包括在半导体结构内形成空隙的方法。 在一些实施例中，空隙可以用作用于分配冷却剂的微结构，用于引导电磁辐射，或用于材料的分离和/或表征。 一些实施例包括其中具有对应于空隙，导管，绝缘结构，半导体结构或导电结构的微结构的结构。

公开(公告)号：US07956416B2

公开(公告)日：2011-06-07

申请号：US12474383

申请日：2009-05-29

Applicant: David H. Wells ,  Eric R. Blomiley

Inventor： David H. Wells ,  Eric R. Blomiley

IPC: H01L21/32

CPC classification number: H01L29/1083 ,  H01L21/3221 ,  H01L27/108 ,  H01L27/10873 ,  H01L27/11 ,  H01L29/7833 ,  H01L29/7849 ,  H01L29/78648 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments include formation of at least one cavity in a first semiconductor material, followed by epitaxially growing a second semiconductor material over the first semiconductor material and bridging across the at least one cavity. The cavity may be left open, or material may be provided within the cavity. The material provided within the cavity may be suitable for forming, for example, one or more of electromagnetic radiation interaction components, transistor gates, insulative structures, and coolant structures. Some embodiments include one or more of transistor devices, electromagnetic radiation interaction components, transistor devices, coolant structures, insulative structures and gas reservoirs.

Abstract translation: 一些实施例包括在第一半导体材料中形成至少一个空腔，随后在第一半导体材料上外延生长第二半导体材料并桥接穿过至少一个空腔。 空腔可以保持打开，或者可以在空腔内提供材料。 设置在空腔内的材料可适用于形成例如电磁辐射相互作用部件，晶体管栅极，绝缘结构和冷却剂结构中的一个或多个。 一些实施例包括晶体管器件，电磁辐射相互作用元件，晶体管器件，冷却剂结构，绝缘结构和气体储存器中的一个或多个。

公开(公告)号：US07709341B2

公开(公告)日：2010-05-04

申请号：US11445544

申请日：2006-06-02

Applicant: Janos Fucsko ,  David H. Wells ,  Patrick Flynn ,  Whonchee Lee

Inventor： Janos Fucsko ,  David H. Wells ,  Patrick Flynn ,  Whonchee Lee

IPC: H01L21/20

CPC classification number: H01L21/30608 ,  H01L21/302 ,  H01L21/31116 ,  H01L21/76232 ,  H01L29/66818

Abstract: A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The single crystal silicon substrate is exposed to an anisotropic etchant that undercuts the single crystal silicon. By controlling the length of the etch, single crystal silicon islands or smooth vertical walls in the single crystal silicon may be created.

Abstract translation: 单晶硅蚀刻方法包括提供其中具有至少一个沟槽的单晶硅衬底。 将单晶硅衬底暴露于底切单晶硅的各向异性蚀刻剂。 通过控制蚀刻的长度，可以产生单晶硅中的单晶硅岛或平滑的垂直壁。

公开(公告)号：US20090271758A1

公开(公告)日：2009-10-29

申请号：US12498951

申请日：2009-07-07

Applicant: David H. Wells

Inventor： David H. Wells

IPC: G06F17/50

CPC classification number: H01L45/1691 ,  H01L21/0337 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76885 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/1052 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/115 ,  H01L45/06 ,  H01L45/085 ,  H01L45/124 ,  H01L45/144 ,  H01L45/149 ,  H01L45/1608 ,  H01L45/1683

Abstract: Methods of forming arrays of small, densely spaced holes or pillars for use in integrated circuits are disclosed. Various pattern transfer and etching steps can be used, in combination with pitch-reduction techniques, to create densely-packed features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed patterns of crossing elongate features with pillars at the intersections. Spacers are simultaneously applied to sidewalls of both sets of crossing lines to produce a pitch-doubled grid pattern. The pillars facilitate rows of spacers bridging columns of spacers.

Abstract translation: 公开了形成集成电路中使用的小密集间隔开的孔或柱的阵列的方法。 可以使用各种图案转移和蚀刻步骤，结合减音技术来产生密集包装的特征。 常规的光刻步骤可以与俯仰减小技术组合使用，以在交叉处形成具有柱的交叉细长特征的叠加图案。 间隔件同时应用于两组交叉线的侧壁以产生间距倍增的网格图案。 这些支柱有利于排列隔离柱的柱。

公开(公告)号：US07601608B2

公开(公告)日：2009-10-13

申请号：US11490619

申请日：2006-07-21

Applicant: David H. Wells

Inventor： David H. Wells

IPC: H01L21/8242

CPC classification number: H01L27/10808 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885

Abstract: A method of forming a buried digit line is disclosed. Sacrificial spacers are formed along the sidewalls of an isolation trench, which is then filled with a sacrificial material. One spacer is masked while the other spacer is removed and an etch step into the substrate beneath the removed spacer forms an isolation window. Insulating liners are then formed along the sidewalls of the emptied trench, including into the isolation window. A digit line recess is then formed through the bottom of the trench between the insulating liners, which double as masks to self-align this etch. The digit line recess is then filled with metal and recessed back, with an optional prior insulating element deposited and recessed back in the bottom of the recess.

Abstract translation: 公开了一种形成掩埋数字线的方法。 牺牲隔离物沿着隔离沟槽的侧壁形成，然后用牺牲材料填充。 一个间隔物被屏蔽，而另一个间隔物被去除，并且在去除的间隔物下方的衬底中的蚀刻步骤形成隔离窗。 然后，绝缘衬垫沿着排空的沟槽的侧壁形成，包括进入隔离窗。 然后在绝缘衬垫之间通过沟槽的底部形成数字线凹槽，这两个绝缘衬垫作为掩模加倍以自对准该蚀刻。 然后，数字线凹槽填充有金属和凹进的后部，并且具有可选的预先绝缘元件，并且沉积在凹部的底部中。

公开(公告)号：US20090095997A1

公开(公告)日：2009-04-16

申请号：US12337292

申请日：2008-12-17

Applicant: David H. Wells ,  Du Li

Inventor： David H. Wells ,  Du Li

IPC: H01L29/788 ,  H01L29/94

CPC classification number: H01L29/788 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/02639 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/045 ,  H01L29/66795 ,  H01L29/7851

Abstract: Memory cell structures, including PSOIs, NANDs, NORs, FinFETs, etc., and methods of fabrication have been described that include a method of epitaxial silicon growth. The method includes providing a silicon layer on a substrate. A dielectric layer is provided on the silicon layer. A trench is formed in the dielectric layer to expose the silicon layer, the trench having trench walls in the direction. The method includes epitaxially growing silicon between trench walls formed in the dielectric layer.

Abstract translation: 已经描述了包括外延硅生长的方法的包括PSOI，NAND，NOR，FinFET等的存储单元结构和制造方法。 该方法包括在衬底上提供硅层。 在硅层上提供介电层。 在电介质层中形成沟槽以暴露硅层，沟槽具有沿<100>方向的沟槽壁。 该方法包括在形成在电介质层中的沟槽壁之间外延生长硅。

公开(公告)号：US20080254627A1

公开(公告)日：2008-10-16

申请号：US12122974

申请日：2008-05-19

Applicant: David H. Wells

Inventor： David H. Wells

IPC: H01L21/308

CPC classification number: H01L21/31144 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/76838 ,  H01L27/105 ,  Y10S438/946 ,  Y10S438/947

Abstract: Variations in the pitch of features formed using pitch multiplication are minimized by separately forming at least two sets of spacers. Mandrels are formed and the positions of their sidewalls are measured. A first set of spacers is formed on the sidewalls. The critical dimension of the spacers is selected based upon the sidewall positions, so that the spacers are centered at desired positions. The mandrels are removed and the spacers are used as mandrels for a subsequent spacer formation. A second material is then deposited on the first set of spacers, with the critical dimensions of the second set of spacers chosen so that these spacers are also centered at their desired positions. The first set of spacers is removed and the second set is used as a mask for etching a substrate. By selecting the critical dimensions of spacers based partly on the measured position of mandrels, the pitch of the spacers can be finely controlled.

Abstract translation: 通过分开形成至少两组间隔物来最小化使用间距倍增形成的特征的间距的变化。 形成心轴并测量其侧壁的位置。 第一组间隔件形成在侧壁上。 基于侧壁位置选择间隔物的临界尺寸，使得间隔件居中在期望的位置。 去除心轴，并且间隔件用作后续间隔物形成的心轴。 然后将第二材料沉积在第一组间隔物上，其中第二组间隔物的临界尺寸选择为使得这些间隔物也位于其所需位置的中心。 去除第一组间隔物，将第二组用作蚀刻基底的掩模。 通过部分地基于心轴的测量位置选择间隔物的临界尺寸，可以精细地控制间隔物的间距。

公开(公告)号：US20080188051A1

公开(公告)日：2008-08-07

申请号：US11704466

申请日：2007-02-07

Applicant: David H. Wells

Inventor： David H. Wells

IPC: H01L21/20 ,  H01L21/336

CPC classification number: H01L21/764 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/0265 ,  H01L21/2015

Abstract: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.

Abstract translation: 一些实施例包括在半导体结构内形成空隙的方法。 在一些实施例中，空隙可以用作用于分配冷却剂的微结构，用于引导电磁辐射，或用于材料的分离和/或表征。 一些实施例包括其中具有对应于空隙，导管，绝缘结构，半导体结构或导电结构的微结构的结构。