公开(公告)号：US20150108619A1

公开(公告)日：2015-04-23

申请号：US14505154

申请日：2014-10-02

Applicant: Applied Materials, Inc.

Inventor： Srinivas D. NEMANI

IPC: H01L21/308 ,  H01L29/02

CPC classification number: H01L21/0337

Abstract: Embodiments of the present disclosure provide methods for patterning rectangular features with a sequence of lithography, atomic layer deposition (ALD) and etching. Embodiment of the present disclosure includes forming first line clusters along a first direction and second line clusters over the first line clusters in a direction traversing the first direction. The first and second line clusters both include core lines formed from a core material, spacers formed from first and second materials by ALD and etching. After formation of the first and second line clusters, rectangular openings can be formed by selectively etching one or two of the core material, the first material or the second material.

Abstract translation: 本公开的实施例提供了利用光刻，原子层沉积（ALD）和蚀刻的顺序图案化矩形特征的方法。 本公开的实施例包括沿着第一方向形成第一线簇并且在穿过第一方向的方向上在第一线群上形成第二线群。 第一和第二线簇都包括由芯材形成的芯线，由第一和第二材料通过ALD和蚀刻形成的间隔物。 在形成第一和第二线簇之后，可以通过选择性地蚀刻芯材，第一材料或第二材料中的一个或两个来形成矩形开口。

公开(公告)号：US20150099360A1

公开(公告)日：2015-04-09

申请号：US14505167

申请日：2014-10-02

Applicant: Applied Materials, Inc.

Inventor： Ellie Y. YIEH ,  Ludovic GODET ,  Srinivas D. NEMANI

IPC: H01L21/8234 ,  H01L29/51 ,  H01L21/263 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L21/823462 ,  H01L21/0415 ,  H01L21/046 ,  H01L21/2236 ,  H01L21/2253 ,  H01L21/28185 ,  H01L21/31155 ,  H01L21/823431 ,  H01L29/66545 ,  H01L29/66803 ,  H01L29/6681 ,  H01L29/785

Abstract: Embodiments described herein generally relate to methods for forming gate structures. Various processes may be performed on a gate dielectric material to reduce the K value of the dielectric material. The gate dielectric having a reduced K value may provide for reduced parasitic capacitance and an overall reduced capacitance. The gate dielectric may be modified without thermodynamic constraint.

Abstract translation: 本文描述的实施例通常涉及用于形成栅极结构的方法。 可以在栅极电介质材料上进行各种工艺以降低电介质材料的K值。 具有减小的K值的栅极电介质可以提供减小的寄生电容和整体减小的电容。 可以在没有热力学约束的情况下修改栅极电介质。

公开(公告)号：US20150064921A1

公开(公告)日：2015-03-05

申请号：US14015557

申请日：2013-08-30

Applicant: Applied Materials, Inc.

Inventor： Srinivas D. NEMANI ,  Sean S. KANG ,  Jeremiah T. P. PENDER ,  Chia-Ling KAO ,  Sergey G. BELOSTOTSKIY ,  Lina ZHU

IPC: H01L21/311

CPC classification number: H01L21/31116 ,  H01J37/32357 ,  H01J37/3244 ,  H01J37/32715 ,  H01J2237/334 ,  H01L21/3081 ,  H01L21/68742

Abstract: Methods for etching a material layer disposed on the substrate using a low temperature etching process along with a subsequent low temperature plasma annealing process are provided. In one embodiment, a method for etching a material layer disposed on a substrate includes transferring a substrate having a material layer disposed thereon into an etching processing chamber, supplying an etching gas mixture into the processing chamber, remotely generating a plasma in the etching gas mixture to etch the material layer disposed on the substrate, and plasma annealing the material layer at a substrate temperature less than 100 degrees Celsius.

Abstract translation: 提供了使用低温蚀刻工艺以及随后的低温等离子体退火工艺来蚀刻设置在基板上的材料层的方法。 在一个实施例中，用于蚀刻设置在基板上的材料层的方法包括将其上设置有材料层的基板转印到蚀刻处理室中，将蚀刻气体混合物供应到处理室中，在蚀刻气体混合物中远程产生等离子体 蚀刻设置在基板上的材料层，以及在低于100摄氏度的衬底温度下对材料层进行等离子体退火。

公开(公告)号：US20230377958A1

公开(公告)日：2023-11-23

申请号：US18228393

申请日：2023-07-31

Applicant: Applied Materials, Inc.

Inventor： Keith Tatseun WONG ,  Srinivas D. NEMANI ,  Ellie Y. YIEH

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/285

CPC classification number: H01L21/76834 ,  H01L23/5329 ,  H01L21/28562 ,  H01L21/76832

Abstract: Methods for forming a transition metal material on a substrate and thermal processing such metal containing material in a cluster processing system are provided. In one embodiment, a method for a device structure for semiconductor devices includes forming a two-dimensional transition metal dichalcogenide layer on a substrate in a first processing chamber disposed in a cluster processing system, thermally treating the two-dimensional transition metal dichalcogenide layer to form a treated metal layer in a second processing chamber disposed in the cluster processing system, and forming a capping layer on the treated metal layer in a third processing chamber disposed in the cluster processing system.

公开(公告)号：US20220269179A1

公开(公告)日：2022-08-25

申请号：US17668065

申请日：2022-02-09

Applicant: Applied Materials, Inc.

Inventor： Douglas A. BUCHBERGER, JR. ,  Dmitry LUBOMIRSKY ,  John O. DUKOVIC ,  Srinivas D. NEMANI

IPC: G03F7/38

Abstract: A method and apparatus for applying an electric field and/or a magnetic field to a photoresist layer without air gap intervention during photolithography processes is provided herein. The method and apparatus include an immersion bake head, which includes an electrode and is configured to be alternated between a hot pedestal and a cold pedestal. The immersion bake head serves as a substrate carrier and applies an electric field to the substrate. The immersion bake head additionally serves to provide and remove process fluid from the substrate using a plurality of fluid conduits.

公开(公告)号：US20220260917A1

公开(公告)日：2022-08-18

申请号：US17176108

申请日：2021-02-15

Applicant: Applied Materials, Inc.

Inventor： Douglas A. BUCHBERGER, JR. ,  Dmitry LUBOMIRSKY ,  John O. DUKOVIC ,  Srinivas D. NEMANI

IPC: G03F7/38

Abstract: A method and apparatus for applying an electric field and/or a magnetic field to a photoresist layer without air gap intervention during photolithography processes is provided herein. The method and apparatus include an electrode assembly and a base assembly. The electrode assembly includes a permeable electrode. The base assembly includes one or more process fluid channels disposed around a circumference of the substrate support surface and configured to fill a process volume with a process fluid. The electrode assembly is configured to apply an electric field to a substrate disposed within the process volume.

公开(公告)号：US20210193461A1

公开(公告)日：2021-06-24

申请号：US17192882

申请日：2021-03-04

Applicant: Applied Materials, Inc.

Inventor： Bhargav S. CITLA ,  Mei-Yee SHEK ,  Srinivas D. NEMANI

IPC: H01L21/02 ,  C23C14/02 ,  C23C14/06 ,  H01L21/033 ,  C23C14/35

Abstract: Embodiments described herein provide for post deposition anneal of a substrate, having an amorphous carbon layer deposited thereon, to desirably reduce variations in local stresses thereacross. In one embodiment, a method of processing a substrate includes positioning a substrate, having an amorphous carbon layer deposited thereon, in a first processing volume, flowing an anneal gas into the first processing volume, heating the substrate to an anneal temperature of not more than about 450° C., and maintaining the substrate at the anneal temperature for about 30 seconds or more. Herein, the amorphous carbon layer was deposited on the substrate using a method which included positioning the substrate on a substrate support disposed in a second processing volume, flowing a processing gas into the second processing volume, applying pulsed DC power to a carbon target disposed in the second processing volume, forming a plasma of the processing gas, and depositing the amorphous carbon layer on the substrate.

公开(公告)号：US20200343103A1

公开(公告)日：2020-10-29

申请号：US16926422

申请日：2020-07-10

Applicant: Applied Materials, Inc.

Inventor： Adib M. KHAN ,  Qiwei LIANG ,  Sultan MALIK ,  Srinivas D. NEMANI

IPC: H01L21/447 ,  C23C16/452 ,  H01L21/67

Abstract: The present disclosure relates to high pressure processing apparatus for semiconductor processing. The apparatus described herein include a high pressure process chamber and a containment chamber surrounding the process chamber. A high pressure fluid delivery module is in fluid communication with the high pressure process chamber and is configured to deliver a high pressure fluid to the process chamber.

公开(公告)号：US20200303183A1

公开(公告)日：2020-09-24

申请号：US16802290

申请日：2020-02-26

Applicant: Applied Materials, Inc.

Inventor： Christopher AHLES ,  Jong CHOI ,  Andrew C. KUMMEL ,  Keith Tatseun WONG ,  Srinivas D. NEMANI

IPC: H01L21/02 ,  C23C16/455 ,  C23C16/40

Abstract: Methods for depositing a metal containing material formed on a certain material of a substrate using an atomic layer deposition process for semiconductor applications are provided. In one example, a method of forming a metal containing material on a substrate comprises pulsing a first gas precursor comprising a metal containing precursor to a surface of a substrate, pulsing a second gas precursor comprising a carboxylic acid to the surface of the substrate, and forming a metal containing material selectively on a first material of the substrate. In another example, a method of forming a metal containing material on a substrate includes selectively forming a metal containing layer on a silicon material or a metal material on a substrate than on an insulating material on the substrate by an atomic layer deposition process by alternatively supplying a metal containing precursor and a water free precursor to the substrate.

公开(公告)号：US20200185260A1

公开(公告)日：2020-06-11

申请号：US16706115

申请日：2019-12-06

Applicant: Applied Materials, Inc.

Inventor： Sultan MALIK ,  Srinivas D. NEMANI ,  Qiwei LIANG ,  Adib M. KHAN

IPC: H01L21/687 ,  H01L21/673

Abstract: Embodiments of the disclosure relate to an apparatus and method for processing semiconductor substrates. In one embodiment, a processing system is disclosed. The processing system includes an outer chamber that surrounds an inner chamber. The inner chamber includes a substrate support upon which a substrate is positioned during processing. The inner chamber is configured to have an internal volume that, when isolated from an internal volume of the outer chamber, is changeable such that the pressure within the internal volume of the inner chamber may be varied.