SELF-LIMITING CHEMICAL VAPOR DEPOSITION AND ATOMIC LAYER DEPOSITION METHODS
    1.
    发明申请
    SELF-LIMITING CHEMICAL VAPOR DEPOSITION AND ATOMIC LAYER DEPOSITION METHODS 有权
    自制化学蒸气沉积和原子层析沉积法

    公开(公告)号:US20150162182A1

    公开(公告)日:2015-06-11

    申请号:US14561525

    申请日:2014-12-05

    Abstract: Methods for depositing silicon on a semiconductor or metallic surface include cycling dosing of silane and chlorosilane precursors at a temperature between 50° C. and 300° C., and continuing cycling between three and twenty three cycles until the deposition self-limits via termination of surface sites with Si—H groups. Methods of layer formation include depositing a chlorosilane onto a substrate to form a first layer, wherein the substrate is selected from the group consisting of InxGa1-xAs, InxGa1-xSb, InxGa1-xN, SiGe, and Ge, wherein X is between 0.1 and 0.99. The methods may include pulsing a silane to form a silicon monolayer and cycling dosing of the chlorosilane and the silane. Layered compositions include a first layer selected from the group consisting of InxGa1-xAs, InxGa1-xSb, InxGa1-xN, SiGe, and Ge, wherein X is between 0.1 and 0.99, and a second layer, wherein the second layer comprises Si—H and Si—OH.

    Abstract translation: 在半导体或金属表面上沉积硅的方法包括在50℃和300℃之间的温度下循环给予硅烷和氯代硅烷前体,并在三到二十三个循环之间持续循环,直到通过终止 具有Si-H基团的表面位点。 层形成方法包括在衬底上沉积氯硅烷以形成第一层,其中衬底选自In x Ga 1-x As,In x Ga 1-x Sb,In x Ga 1-x N,Si Ge和Ge,其中X在0.1和 0.99。 所述方法可以包括脉动硅烷以形成硅单层并循环给予氯硅烷和硅烷。 层状组合物包括选自In x Ga 1-x As,In x Ga 1-x Sb,In x Ga 1-x N,Si Ge和Ge中的第一层,其中X为0.1至0.99,第二层为第二层,其中第二层包含Si-H 和Si-OH。

    CVD SILICON MONOLAYER FORMATION METHOD AND GATE OXIDE ALD FORMATION ON SEMICONDUCTOR MATERIALS

    公开(公告)号:US20180033610A1

    公开(公告)日:2018-02-01

    申请号:US15727351

    申请日:2017-10-06

    Abstract: Methods for depositing silicon include cycling dosing between 1 and 100 cycles of one or more first chlorosilane precursors on a III-V surface at a temperature between 300° C. and 500° C. to form a first layer. Methods may include desorbing chlorine from the first layer by treating the first layer with atomic hydrogen to form a second layer. Methods may include forming a silicon multilayer on the second layer by cycling dosing between 1 and 100 cycles of one or more second chlorosilane precursors and atomic hydrogen at a temperature between 300° C. and 500° C. A layered composition includes a first layer selected from the group consisting of InxGa1-xAs, InxGa1-xSb, InxGa1-xN, SiGe, and Ge, wherein X is between 0.1 and 0.99, and a second layer, wherein the second layer comprises Si—H and Si—OH.

    HIGH SELECTIVITY ATOMIC LATER DEPOSITION PROCESS

    公开(公告)号:US20200303183A1

    公开(公告)日:2020-09-24

    申请号:US16802290

    申请日:2020-02-26

    Abstract: Methods for depositing a metal containing material formed on a certain material of a substrate using an atomic layer deposition process for semiconductor applications are provided. In one example, a method of forming a metal containing material on a substrate comprises pulsing a first gas precursor comprising a metal containing precursor to a surface of a substrate, pulsing a second gas precursor comprising a carboxylic acid to the surface of the substrate, and forming a metal containing material selectively on a first material of the substrate. In another example, a method of forming a metal containing material on a substrate includes selectively forming a metal containing layer on a silicon material or a metal material on a substrate than on an insulating material on the substrate by an atomic layer deposition process by alternatively supplying a metal containing precursor and a water free precursor to the substrate.

    LOW TEMPERATURE ALD ON SEMICONDUCTOR AND METALLIC SURFACES
    6.
    发明申请
    LOW TEMPERATURE ALD ON SEMICONDUCTOR AND METALLIC SURFACES 审中-公开
    半导体和金属表面的低温ALD

    公开(公告)号:US20170040158A1

    公开(公告)日:2017-02-09

    申请号:US15230197

    申请日:2016-08-05

    CPC classification number: H01L21/0228 H01L21/0217 H01L21/02211

    Abstract: The present disclosure provides for semiconductor fabrication processes that include atomic layer depositions. Embodiments described herein provide for formation of a diffusion barrier or gate dielectric layer in preparation for subsequent ALD on semiconductor surfaces. More specifically, embodiments of the present disclosure provide for the formation of fin field effect transistor (FinFET) and metal oxide semiconductor field effect transistor (MOSFET) devices utilizing improved ALD processes.

    Abstract translation: 本公开提供了包括原子层沉积的半导体制造工艺。 本文描述的实施例提供了扩散阻挡层或栅极介电层的形成,以准备半导体表面上的随后的ALD。 更具体地,本公开的实施例提供了利用改进的ALD工艺形成鳍式场效应晶体管(FinFET)和金属氧化物半导体场效应晶体管(MOSFET)器件。

    SELECTIVE DEPOSITION OF METAL OXIDE BY PULSED CHEMICAL VAPOR DEPOSITION

    公开(公告)号:US20230122224A1

    公开(公告)日:2023-04-20

    申请号:US18072392

    申请日:2022-11-30

    Abstract: Embodiments described and discussed herein provide methods for selectively depositing a metal oxides on a substrate. In one or more embodiments, methods for forming a metal oxide material includes positioning a substrate within a processing chamber, where the substrate has passivated and non-passivated surfaces, exposing the substrate to a first metal alkoxide precursor to selectively deposit a first metal oxide layer on or over the non-passivated surface, and exposing the substrate to a second metal alkoxide precursor to selectively deposit a second metal oxide layer on the first metal oxide layer. The method also includes sequentially repeating exposing the substrate to the first and second metal alkoxide precursors to produce a laminate film containing alternating layers of the first and second metal oxide layers. Each of the first and second metal alkoxide precursors contains a different metal selected from titanium, zirconium, hafnium, aluminum, or lanthanum.

    SELECTIVE DEPOSITION OF METAL OXIDE BY PULSED CHEMICAL VAPOR DEPOSITION

    公开(公告)号:US20210317573A1

    公开(公告)日:2021-10-14

    申请号:US16902665

    申请日:2020-06-16

    Abstract: Embodiments described and discussed herein provide methods for selectively depositing a metal oxides on a substrate. In one or more embodiments, methods for forming a metal oxide material includes positioning a substrate within a processing chamber, where the substrate has passivated and non-passivated surfaces, exposing the substrate to a first metal alkoxide precursor to selectively deposit a first metal oxide layer on or over the non-passivated surface, and exposing the substrate to a second metal alkoxide precursor to selectively deposit a second metal oxide layer on the first metal oxide layer. The method also includes sequentially repeating exposing the substrate to the first and second metal alkoxide precursors to produce a laminate film containing alternating layers of the first and second metal oxide layers. Each of the first and second metal alkoxide precursors contain different types of metals which are selected from titanium, zirconium, hafnium, aluminum, or lanthanum.

    CVD SILICON MONOLAYER FORMATION METHOD AND GATE OXIDE ALD FORMATION ON III-V MATERIALS
    10.
    发明申请
    CVD SILICON MONOLAYER FORMATION METHOD AND GATE OXIDE ALD FORMATION ON III-V MATERIALS 有权
    CVD硅酸盐单层形成方法和III-V材料上的氧化铝形成

    公开(公告)号:US20150303058A1

    公开(公告)日:2015-10-22

    申请号:US14686870

    申请日:2015-04-15

    Abstract: Methods for depositing silicon include cycling dosing between 1 and 100 cycles of one or more first chlorosilane precursors on a III-V surface at a temperature between 300° C. and 500° C. to form a first layer. Methods may include desorbing chlorine from the first layer by treating the first layer with atomic hydrogen to form a second layer. Methods may include forming a silicon multilayer on the second layer by cycling dosing between 1 and 100 cycles of one or more second chlorosilane precursors and atomic hydrogen at a temperature between 300° C. and 500° C. A layered composition includes a first layer selected from the group consisting of InxGa1-xAs, InxGa1-xSb, InxGa1-xN, SiGe, and Ge, wherein X is between 0.1 and 0.99, and a second layer, wherein the second layer comprises Si—H and Si—OH.

    Abstract translation: 沉积硅的方法包括在300℃和500℃之间的温度下在III-V表面上循环给予1至100个循环的一种或多种第一氯硅烷前体以形成第一层。 方法可以包括通过用原子氢处理第一层来形成第二层从第一层解吸氯。 方法可以包括通过在300℃和500℃之间的温度下循环给予1至100个循环的一个或多个第二氯硅烷前体和原子氢来在第二层上形成硅多层。分层组合物包括选择的第一层 来自由In x Ga 1-x As,In x Ga 1-x Sb,In x Ga 1-x N,SiGe和Ge组成的组,其中X为0.1至0.99,第二层为第二层,其中第二层包含Si-H和Si-OH。

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