公开(公告)号：US5586005A

公开(公告)日：1996-12-17

申请号：US405069

申请日：1995-03-16

Applicant: Thomas M. Cipolla ,  Paul W. Coteus

Inventor： Thomas M. Cipolla ,  Paul W. Coteus

IPC: H01L23/367 ,  H01L23/40 ,  H05K7/20

CPC classification number: H01L23/40 ,  H01L23/3677 ,  H01L23/4093 ,  H01L2924/0002 ,  Y10S411/907 ,  Y10T24/309 ,  Y10T24/42 ,  Y10T29/49876

Abstract: The invention employs a post type fastening member that provides, at one end, an insertion friction connection to the circuit card and at the other end, extending through the heat sink, a compression spring means that urges the heat sink toward the circuit card. A plurality of the post type fasteners are positioned around the periphery of the chip package to retain the heat sink parallel to the circuit card and compressing the chip package. The packaging structure of the invention permits larger area heat sinks than the chip package area to be supported by the circuit card with the only relationship with the chip being that of a compression thermal transfer contact and radiation shield.

Abstract translation: 本发明采用柱式紧固件，其一端提供与电路卡的插入摩擦​​连接，并且在另一端提供延伸穿过散热器的压缩弹簧装置，其将散热片朝向电路卡推动。 多个柱形紧固件围绕芯片封装的周边定位，以将热沉平行于电路卡并压缩芯片封装。 本发明的封装结构允许比芯片封装区域更大的区域散热器由电路卡支撑，与芯片的唯一关系是压缩热转印触点和辐射屏蔽的关系。

公开(公告)号：US5480841A

公开(公告)日：1996-01-02

申请号：US302084

申请日：1994-09-07

Applicant: Harry R. Bickford ,  Paul W. Coteus ,  Linda C. Matthew

Inventor： Harry R. Bickford ,  Paul W. Coteus ,  Linda C. Matthew

IPC: H01L23/02 ,  H01L23/10 ,  H01L23/495 ,  H01L23/498 ,  H01L23/50 ,  H05K3/34 ,  H01L21/60

CPC classification number: H05K3/3426 ,  H01L23/4951 ,  H01L23/49534 ,  H01L23/49572 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/48 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/4824 ,  H01L2224/4826 ,  H01L2224/48464 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/3011 ,  H01L2924/351 ,  H05K2201/10568 ,  H05K2201/10681 ,  H05K2201/10689 ,  Y02P70/613

Abstract: A process of providing an external wiring and connecting package for a semiconductor chip wherein the chip is a major contributor to the strength of the package. External contacts and wiring are provided by a multilayer wiring member that may include a mesh ground plane with embedded power bus layer over a conductor layer for expansion mismatch control and impedance control, a protective encapsulation covers the bonds from the wiring conductors to the chip, and external contact connections employ fused metal through the contact members.

Abstract translation: 提供用于半导体芯片的外部布线和连接封装的工艺，其中芯片是封装强度的主要贡献者。 外部触点和布线由多层布线构件提供，多层布线构件可以包括在导体层上的嵌入式电源总线层的网格接地面，用于扩展失配控制和阻抗控制，保护封装覆盖从布线导体到芯片的接合，以及 外部接触连接通过接触构件使用熔融金属。

公开(公告)号：US5266520A

公开(公告)日：1993-11-30

申请号：US992114

申请日：1992-12-17

Applicant: Thomas M. Cipolla ,  Paul W. Coteus ,  Robert H. Katyl ,  Robert J. Kelleher ,  Paul A. Moskowitz

Inventor： Thomas M. Cipolla ,  Paul W. Coteus ,  Robert H. Katyl ,  Robert J. Kelleher ,  Paul A. Moskowitz

IPC: H01L21/60 ,  H01L23/485 ,  H01L21/44

CPC classification number: H01L24/10 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/14133 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  Y10T29/49144

Abstract: In joining conductors at different levels on a carrier to contact locations on a planar substrate, mound shaped connections are employed, with the height of each mound shaped connection extending to the level of the particular conductor to which it is bonded. The mound shaped connections are formed using planar processes of controlled volume deposition, surface tension shaping on reflow, and physical deformation. The height of the mound shaped connections are calculated empirically from the volume deposited bounded by the substrate pad after surface tension limits the slump on reflowing.

Abstract translation: 在将载体上的不同级别的导体接合以接触平面基板上的位置时，使用墩形连接，每个墩形连接的高度延伸到与其结合的特定导体的高度。 使用受控体积沉积的平面过程，回流时的表面张力整形和物理变形来形成土堆形连接。 在表面张力限制回流后的坍落度之后，根据由衬底焊盘界定的体积经验地计算出土墩形连接的高度。

公开(公告)号：US5173763A

公开(公告)日：1992-12-22

申请号：US654178

申请日：1991-02-11

Applicant: Thomas M. Cipolla ,  Paul W. Coteus ,  Robert H. Katyl ,  Robert J. Kelleher ,  Paul A. Moskowitz

Inventor： Thomas M. Cipolla ,  Paul W. Coteus ,  Robert H. Katyl ,  Robert J. Kelleher ,  Paul A. Moskowitz

IPC: H01L21/60 ,  H01L23/485

CPC classification number: H01L24/50 ,  H01L24/10 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/14133 ,  H01L2224/14135 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14

Abstract: In joining conductors at different levels on a carrier to contact locations on a planar substrate, mound shaped connections are employed, with the height of each mound shaped connection extending to the level of the particular conductor to which it is bonded. The mound shaped connections are formed using planar processes of controlled volume deposition, surface tension shaping on reflow, and physical deformation. The height of the mound shaped connections are calculated empirically from the volume deposited bounded by the substrate pad after surface tension limits the slump on reflowing.

公开(公告)号：US09137098B2

公开(公告)日：2015-09-15

申请号：US13584300

申请日：2012-08-13

Applicant: Dong Chen ,  Paul W. Coteus ,  Noel A. Eisley ,  Philip Heidelberger ,  Robert M. Senger ,  Yutaka Sugawara

Inventor： Dong Chen ,  Paul W. Coteus ,  Noel A. Eisley ,  Philip Heidelberger ,  Robert M. Senger ,  Yutaka Sugawara

IPC: H04L12/715 ,  H04L12/24

CPC classification number: H04L41/0663 ,  H04L41/12 ,  H04L41/145 ,  H04L45/04

Abstract: According to one embodiment of the present invention, a method of constructing network communication for a grid of node groups is provided, the grid including an M dimensional grid, each node group including N nodes, wherein M is greater than or equal to one and N is greater than one, wherein each node includes a router. The method includes directly connecting each node in each node group to every other node in the node group via intra-group links and directly connecting each node in each node group of the M dimensional grid to a node in each neighboring node group in the M dimensional grid via inter-group links.

Abstract translation: 根据本发明的一个实施例，提供了一种为节点组网格构建网络通信的方法，所述网格包括M维网格，每个节点组包括N个节点，其中M大于或等于1，并且N 大于1，其中每个节点包括路由器。 该方法包括通过组内链路将每个节点组中的每个节点直接连接到节点组中的每个其他节点，并将M维网格的每个节点组中的每个节点直接连接到M维中的每个相邻节点组中的节点 网格通过组间链接。

公开(公告)号：US08909878B2

公开(公告)日：2014-12-09

申请号：US13494280

申请日：2012-06-12

Applicant: Paul W. Coteus ,  Kyu-hyoun Kim

Inventor： Paul W. Coteus ,  Kyu-hyoun Kim

IPC: G06F12/00

CPC classification number: G11C29/26 ,  G06F13/1684 ,  G06F13/1689 ,  G11C29/023 ,  G11C29/028 ,  G11C2029/2602

Abstract: A method and circuit for implementing synchronized memory activities of multiple memory devices being accessed in parallel, and a design structure on which the subject circuit resides are provided. Each memory circuit generates an internal status signal for predefined internal memory activities and provides an output signal coupled to the multiple memory devices. Each memory circuit monitors the generated internal status signal and the output signal of at least one of the multiple memory devices, and responsive to the monitored signals generates a control signal for adjusting operation of its memory activities to synchronize memory activities of the memory devices.

Abstract translation: 一种用于实现并行访问的多个存储器件的同步存储器活动的方法和电路，以及设置有被摄体电路的设计结构。 每个存储器电路产生用于预定义的内部存储器活动的内部状态信号，并提供耦合到多个存储器件的输出信号。 每个存储器电路监视生成的内部状态信号和多个存储器件中的至少一个的输出信号，并且响应于所监视的信号产生用于调整其存储器活动的操作以控制存储器件的存储器活动的控制信号。

公开(公告)号：US08667049B2

公开(公告)日：2014-03-04

申请号：US13566024

申请日：2012-08-03

Applicant: Matthias A. Blumrich ,  Dong Chen ,  George L. Chiu ,  Thomas M. Cipolla ,  Paul W. Coteus ,  Alan G. Gara ,  Mark E. Giampap ,  Philip Heidlberger ,  Gerard V. Kopcsay ,  Lawrence S. Mok ,  Todd E. Takken

Inventor： Matthias A. Blumrich ,  Dong Chen ,  George L. Chiu ,  Thomas M. Cipolla ,  Paul W. Coteus ,  Alan G. Gara ,  Mark E. Giampap ,  Philip Heidlberger ,  Gerard V. Kopcsay ,  Lawrence S. Mok ,  Todd E. Takken

IPC: G06F15/173

CPC classification number: H05K7/20836 ,  F24F11/77 ,  G06F9/52 ,  G06F9/526 ,  G06F15/17381 ,  G06F17/142 ,  G09G5/008 ,  H04L7/0338

Abstract: A novel massively parallel supercomputer of hundreds of teraOPS-scale includes node architectures based upon System-On-a-Chip technology, i.e., each processing node comprises a single Application Specific Integrated Circuit (ASIC). Within each ASIC node is a plurality of processing elements each of which consists of a central processing unit (CPU) and plurality of floating point processors to enable optimal balance of computational performance, packaging density, low cost, and power and cooling requirements. The plurality of processors within a single node individually or simultaneously work on any combination of computation or communication as required by the particular algorithm being solved. The system-on-a-chip ASIC nodes are interconnected by multiple independent networks that optimally maximizes packet communications throughput and minimizes latency. The multiple networks include three high-speed networks for parallel algorithm message passing including a Torus, Global Tree, and a Global Asynchronous network that provides global barrier and notification functions.

Abstract translation: 数百个teraOPS级别的新型大规模并行超级计算机包括基于片上系统技术的节点架构，即每个处理节点包括单个专用集成电路（ASIC）。 在每个ASIC节点内是多个处理元件，每个处理元件由中央处理单元（CPU）和多个浮点处理器组成，以实现计算性能，封装密度，低成本以及功率和冷却​​要求的最佳平衡。 单个节点内的多个处理器单独或同时工作在要解决的特定算法所要求的计算或通信的任何组合上。 片上系统ASIC节点通过多个独立网络互连，从而最大限度地最大限度地提高了分组通信吞吐量并最大限度地减少了延迟。 多个网络包括用于并行算法消息传递的三个高速网络，包括Torus，全局树和提供全局障碍和通知功能的全球异步网络。

公开(公告)号：US08659959B2

公开(公告)日：2014-02-25

申请号：US13567353

申请日：2012-08-06

Applicant: Kyu-Hyoun Kim ,  George L. Chiu ,  Paul W. Coteus ,  Daniel M. Dreps ,  Kevin C. Gower ,  Hillery C. Hunter ,  Charles A. Kilmer ,  Warren E. Maule

Inventor： Kyu-Hyoun Kim ,  George L. Chiu ,  Paul W. Coteus ,  Daniel M. Dreps ,  Kevin C. Gower ,  Hillery C. Hunter ,  Charles A. Kilmer ,  Warren E. Maule

IPC: G11C7/00

CPC classification number: G11C7/1078 ,  G06F11/1028 ,  G11C7/04 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/109 ,  G11C7/22 ,  G11C7/222 ,  G11C11/401 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40615 ,  G11C11/40626 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

Abstract: An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from being written to the memory array in response to the error control coding circuitry detecting an error in the received command. Another memory device includes a programmable preamble. Another memory device includes a fast exit self-refresh mode. Another memory device includes auto refresh function that is controlled by the characteristic device. Another memory device includes an auto refresh function that is controlled by a characteristic of the memory device.

Abstract translation: 具有改进性能，降低功耗和增加可靠性的高级内存。 存储器件包括存储器阵列，用于接收命令和相关联的数据的接收器，用于对接收到的命令执行错误控制检查的差错控制编码电路以及用于防止相关联的数据被响应地写入存储器阵列的数据屏蔽电路 对错误控制编码电路检测接收到的命令中的错误。 另一个存储器件包括可编程序序。 另一存储器件包括快速退出自刷新模式。 另一种存储装置包括由特征装置控制的自动刷新功能。 另一存储器件包括由存储器件的特性控制的自动刷新功能。

公开(公告)号：US20140044015A1

公开(公告)日：2014-02-13

申请号：US13584300

申请日：2012-08-13

Applicant: Dong Chen ,  Paul W. Coteus ,  Noel A. Eisley ,  Philip Heidelberger ,  Robert M. Senger ,  Yutaka Sugawara

Inventor： Dong Chen ,  Paul W. Coteus ,  Noel A. Eisley ,  Philip Heidelberger ,  Robert M. Senger ,  Yutaka Sugawara

IPC: H04L12/28

CPC classification number: H04L41/0663 ,  H04L41/12 ,  H04L41/145 ,  H04L45/04

Abstract: According to one embodiment of the present invention, a method of constructing network communication for a grid of node groups is provided, the grid including an M dimensional grid, each node group including N nodes, wherein M is greater than or equal to one and N is greater than one, wherein each node includes a router. The method includes directly connecting each node in each node group to every other node in the node group via intra-group links and directly connecting each node in each node group of the M dimensional grid to a node in each neighboring node group in the M dimensional grid via inter-group links.

Abstract translation: 根据本发明的一个实施例，提供了一种为节点组网格构建网络通信的方法，所述网格包括M维网格，每个节点组包括N个节点，其中M大于或等于1，并且N 大于1，其中每个节点包括路由器。 该方法包括通过组内链路将每个节点组中的每个节点直接连接到节点组中的每个其他节点，并将M维网格的每个节点组中的每个节点直接连接到M维中的每个相邻节点组中的节点 网格通过组间链接。

公开(公告)号：US08626957B2

公开(公告)日：2014-01-07

申请号：US13101566

申请日：2011-05-05

Applicant: Matthias A. Blumrich ,  Paul W. Coteus ,  Dong Chen ,  Alan Gara ,  Mark E. Giampapa ,  Philip Heidelberger ,  Dirk Hoenicke ,  Todd E. Takken ,  Burkhard D. Steinmacher-Burow ,  Pavlos M. Vranas

Inventor： Matthias A. Blumrich ,  Paul W. Coteus ,  Dong Chen ,  Alan Gara ,  Mark E. Giampapa ,  Philip Heidelberger ,  Dirk Hoenicke ,  Todd E. Takken ,  Burkhard D. Steinmacher-Burow ,  Pavlos M. Vranas

IPC: G06F15/16

CPC classification number: H04L1/08 ,  G06F9/46 ,  G06F11/08 ,  G06F11/1423 ,  H03M13/09 ,  H04L1/0061 ,  H04L1/1607 ,  H04L1/1867 ,  H04L2001/0093 ,  H04L2001/0097

Abstract: A system and method for enabling high-speed, low-latency global collective communications among interconnected processing nodes. The global collective network optimally enables collective reduction operations to be performed during parallel algorithm operations executing in a computer structure having a plurality of the interconnected processing nodes. Router devices are included that interconnect the nodes of the network via links to facilitate performance of low-latency global processing operations at nodes of the virtual network. The global collective network may be configured to provide global barrier and interrupt functionality in asynchronous or synchronized manner. When implemented in a massively-parallel supercomputing structure, the global collective network is physically and logically partitionable according to needs of a processing algorithm.

Abstract translation: 一种用于实现互连处理节点之间的高速，低延迟全局集体通信的系统和方法。 全局集体网络最优地使得能够在具有多个互连处理节点的计算机结构中执行并行算法操作期间执行集体缩减操作。 包括通过链路互连网络节点的路由器设备，以便于在虚拟网络的节点处执行低延迟全局处理操作。 全局集体网络可以被配置为以异步或同步方式提供全局屏障和中断功能。 当在大规模并行超级计算结构中实现时，全局集体网络根据处理算法的需要在物理上和逻辑上可分割。