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    Semiconductor device with test mode circuit
    71.
    发明授权
    Semiconductor device with test mode circuit 有权
    具有测试模式电路的半导体器件

    公开(公告)号：US09201111B2

    公开(公告)日：2015-12-01

    申请号：US13720348

    申请日：2012-12-19

    Applicant: SK hynix Inc.

    Inventor： Yong-Ho Kong

    IPC: G01R31/3187 ,  G01R31/26 ,  G01R31/317

    CPC classification number: G01R31/2607 ,  G01R31/2644 ,  G01R31/31701 ,  G01R31/31724

    Abstract: A semiconductor device includes a plurality of test entry selection units configured to selectively activate a plurality of test entry signals in response to a test entry code, and a plurality of test operation blocks, corresponding to the respective test entry signals, each configured to be reset in response to activation of the corresponding test entry signal to perform a set test operation corresponding to a test selection code.

    Abstract translation: 半导体器件包括多个测试条目选择单元，其被配置为响应于测试条目代码选择性地激活多个测试条目信号，以及多个测试操作块，其对应于相应的测试条目信号，每个测试操作块被配置为被复位 响应于对应的测试条目信号的激活，以执行与测试选择代码相对应的设置测试操作。

    Isolating failing latches using a logic built-in self-test
    73.
    发明授权
    Isolating failing latches using a logic built-in self-test 有权
    使用逻辑内置自检隔离故障锁存器

    公开(公告)号：US09057766B2

    公开(公告)日：2015-06-16

    申请号：US13689044

    申请日：2012-11-29

    Applicant: International Business Machines Corporation

    Inventor： Ra'ed M. Al-omari ,  Michael W. Harper ,  Cindy Phan ,  Mack W. Riley

    IPC: G01R31/28 ,  G01R31/3185 ,  G01R31/3187

    CPC classification number: G01R31/318566 ,  G01R31/318569 ,  G01R31/3187

    Abstract: A mechanism is provided for identifying a failing latch within an integrated circuit device. A test sequence is initiated on a set of scan chains associated with an identified failing multiple input signature register. For each test portion in a set of test portions in the test sequence, a comparison is performed between an output of the multiple input signature register and a corresponding value in a set of expected values. Responsive to determining a match, a value of a counter is incremented. Responsive to a failure to match, incrementing of the counter is stopped, and the value of the counter providing an indication of the failing latch in the integrated circuit device is read out.

    Abstract translation: 提供了用于识别集成电路器件内的故障锁存器的机构。 在与识别的故障多输入签名寄存器相关联的一组扫描链上启动测试序列。 对于测试序列中的一组测试部分中的每个测试部分，在多输入签名寄存器的输出和一组期望值中的对应值之间执行比较。 响应于确定匹配，计数器的值增加。 响应于不匹配，停止计数器的递增，并且读出提供集成电路装置中的故障锁存器指示的计数器的值。

    Test circuit allowing precision analysis of delta performance degradation between two logic chains
    74.
    发明授权
    Test circuit allowing precision analysis of delta performance degradation between two logic chains 有权
    测试电路允许精确分析两个逻辑链之间的delta性能下降

    公开(公告)号：US09052360B2

    公开(公告)日：2015-06-09

    申请号：US13670056

    申请日：2012-11-06

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Andrew Marshall

    IPC: G01R31/3187 ,  G01R31/02 ,  G01R31/26 ,  G01R31/317

    CPC classification number: G01R31/31725

    Abstract: A test circuit for measuring a gate delay as a function of stress is disclosed. The test circuit includes an oscillator, a reference gate chain, a test gate chain, and a counter. The counter measures the difference in propagation delay between the test chain and the reference chain in calibrated oscillator cycles. Differences in test gate delay as a function of applied stress may be measured within the calibration accuracy of the oscillator frequency. The use of the reference gate chain allows a simpler unipolar counter.

    Abstract translation: 公开了一种用于测量作为应力的函数的门延迟的测试电路。 测试电路包括振荡器，参考门链，测试门链和计数器。 该计数器测量校准振荡器周期中测试链和参考链之间传播延迟的差异。 可以在振荡器频率的校准精度内测量作为施加应力的函数的测试门延迟的差异。 参考栅极链的使用允许更简单的单极计数器。

    Parallel scan paths with three bond pads, distributors and collectors
    75.
    发明授权
    Parallel scan paths with three bond pads, distributors and collectors 有权
    具有三个焊盘，分配器和收集器的并行扫描路径

    公开(公告)号：US08941400B2

    公开(公告)日：2015-01-27

    申请号：US14268073

    申请日：2014-05-02

    Applicant: Texas Instruments Incorporated

    Inventor： Lee D. Whetsel

    IPC: G01R31/3187 ,  G01R31/3177 ,  G01R31/317 ,  G01R31/3185 ,  G01R31/319

    CPC classification number: G01R31/2851 ,  G01R31/31715 ,  G01R31/3177 ,  G01R31/318536 ,  G01R31/318555 ,  G01R31/318563 ,  G01R31/31919

    Abstract: An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944) circuits. The scan paths apply stimulus test data to functional circuits (702) on the integrated circuit and receive response test data from the functional circuits. A scan distributor circuit (800) receives serial test data from a peripheral bond pad (802) and distributes it to each parallel scan path. A scan collector circuit (844) collects test data from the parallel scan paths and applies it to a peripheral bond pad (866). This enables more parallel scan paths of shorter length to connect to the functional circuits. The scan distributor and collector circuits can be respectively connected in series to provide parallel connections to more parallel scan paths. Additionally multiplexer circuits (886,890) can selectively connect pairs of scan distributor and collector circuits together. The scan distributor and collector circuits can be formed in core circuits (704). The core circuits then can be connected to other core circuits and functional circuits with simple connections to the parallel scan circuits through the scan distributor and collector circuits.

    Abstract translation: 具有并行扫描路径（824-842,924-942）的集成电路（70）包括一对或一对扫描分配器（800,900）和扫描收集器（844,944）电路。 扫描路径将激励测试数据应用于集成电路上的功能电路（702），并从功能电路接收响应测试数据。 扫描分配器电路（800）从外围接合焊盘（802）接收串行测试数据，并将其分配到每个并行扫描路径。 扫描收集器电路（844）从并行扫描路径收集测试数据并将其应用于外围接合焊盘（866）。 这使得更长的并行扫描路径能够连接到功能电路。 扫描分配器和集电极电路可以分别串联连接以提供并行连接到更平行的扫描路径。 此外，多路复用器电路（886,890）可以选择性地将成对的扫描分配器和集电极电路连接在一起。 扫描分配器和集电极电路可以形成在核心电路（704）中。 然后，核心电路可以通过扫描分配器和集电极电路与并行扫描电路的简单连接连接到其他核心电路和功能电路。

    MONITORING SYSTEM AND VEHICLE
    76.
    发明申请
    MONITORING SYSTEM AND VEHICLE 有权
    监控系统和车辆

    公开(公告)号：US20140333315A1

    公开(公告)日：2014-11-13

    申请号：US14367400

    申请日：2012-12-21

    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA

    Inventor： Hiroyoshi Yamamoto

    IPC: G01R31/3187 ,  G01R31/36

    CPC classification number: G01R31/3187 ,  G01R31/3606 ,  G01R31/362 ,  G01R31/3658

    Abstract: An object is to provide, at low costs, a function for determining whether a monitoring section should execute a self-diagnosis. A monitoring system has a monitoring section for acquiring information on the charge and discharge state of an electric storage device and a determination section for determining the charge and discharge state of the electric storage device on the basis of information acquired by the monitoring section. The determination section has an output section for continuously outputting, to the monitoring section, a stepped signal made up of a High signal and a Low signal, and as well, when the charge and discharge state of the electric storage device has been determined to fall within an allowable range on the basis of the information acquired from the monitoring section, outputs a diagnosis permit signal that is a unique stepped signal having a period different from that before the determination, and when the signal received from the determination section has been determined to be the diagnosis permit signal, the monitoring section executes a self-diagnosis for detecting an abnormal event in the monitoring section.

    Abstract translation: 目的是以低成本提供用于确定监视部分是否应执行自我诊断的功能。 监视系统具有用于获取关于蓄电装置的充电和放电状态的信息的监视部分和用于基于由监视部分获取的信息来确定蓄电装置的充电和放电状态的确定部。 确定部分具有输出部分，用于向监视部​​分连续地输出由高信号和低信号组成的阶梯信号，并且当蓄电装置的充放电状态已被确定为下降时 基于从监视部获取的信息，在允许范围内，输出作为与判断之前不同的周期的唯一阶梯信号的诊断许可信号，并且当从判定部接收到的信号已经被确定为 作为诊断许可信号，监视部执行用于检测监视部中的异常事件的自诊断。

    Capacitive input test method
    77.
    发明授权
    Capacitive input test method 有权
    电容输入测试方法

    公开(公告)号：US08836359B2

    公开(公告)日：2014-09-16

    申请号：US13144036

    申请日：2010-01-12

    Applicant: Mathias Krauss ,  Sam Koblenski

    Inventor： Mathias Krauss ,  Sam Koblenski

    IPC: G01R31/3187 ,  H03M1/10 ,  H03M1/12

    CPC classification number: H03M1/109 ,  H03M1/12

    Abstract: Method and system are provided for evaluating linearity of a capacitive-to-digital converter (CDC) of a capacitive sensor integrated circuit chip. The evaluating employs multiple test capacitors, which may be on-chip with the CDC, and includes: obtaining capacitance values for the multiple test capacitors and parasitic capacitances of a first input A and a second input B to the capacitive-to-digital converter; applying the multiple test capacitors in multiple permutations to the first input A and the second input B, and for each of at least some permutations, determining an error between an expected output of the CDC using the obtained capacitance values and an actual measured output of the CDC; and determining linearity error for the CDC using the determined errors for the permutations of applying the multiple test capacitors to the first input A and the second input B of the CDC.

    Abstract translation: 提供了用于评估电容式传感器集成电路芯片的电容 - 数字转换器（CDC）的线性度的方法和系统。 该评估采用多个测试电容器，其可以与CDC在芯片上，并且包括：获得多个测试电容器的电容值和第一输入端A和第二输入端B到电容 - 数字转换器的寄生电容; 将多个测试电容器以多个排列施加到第一输入端A和第二输入端B，并且对于至少一些排列中的每一个，使用所获得的电容值确定CDC的期望输出之间的误差和 CDC; 以及使用所确定的用于将多个测试电容器施加到CDC的第一输入A和第二输入B的排列的误差来确定CDC的线性误差。

    Semiconductor device and abnormality prediction method thereof
    79.
    发明授权
    Semiconductor device and abnormality prediction method thereof 有权
    半导体装置及其异常预测方法

    公开(公告)号：US08742779B2

    公开(公告)日：2014-06-03

    申请号：US12789933

    申请日：2010-05-28

    Applicant: Atsushi Takahashi ,  Hiroyuki Kii

    Inventor： Atsushi Takahashi ,  Hiroyuki Kii

    IPC: G01R31/3187

    CPC classification number: G01R31/31703 ,  G06F11/1641

    Abstract: A semiconductor device includes a first CPU, a second CPU having a configuration that is the same as or comparable to a configuration of the first CPU, and a comparator that compares an output of the first CPU with an output of the second CPU. The second CPU is made so as to have a lower operating margin than the first CPU. By supplying a same signal to the first CPU and the second CPU and then detecting a mismatch between the outputs of the first CPU and the second CPU as a result of comparison, the abnormality is predicted. The semiconductor device includes a reset control circuit that resets the device when the result of comparison by the comparator indicates an error.

    Abstract translation: 半导体器件包括第一CPU，具有与第一CPU的配置相同或相当的配置的第二CPU以及将第一CPU的输出与第二CPU的输出进行比较的比较器。 第二个CPU的运行裕度低于第一个CPU。 通过向第一CPU和第二CPU提供相同的信号，然后作为比较结果检测第一CPU和第二CPU的输出之间的不匹配，则预测该异常。 半导体器件包括复位控制电路，当比较器的结果指示错误时复位器件。

    Methods for defect testing of externally accessible integrated circuit interconnects
    80.
    发明授权
    Methods for defect testing of externally accessible integrated circuit interconnects 有权
    外部可访问的集成电路互连的缺陷测试方法

    公开(公告)号：US08736291B2

    公开(公告)日：2014-05-27

    申请号：US13183931

    申请日：2011-07-15

    Applicant: Yoshinori Fujiwara ,  Masayoshi Nomura

    Inventor： Yoshinori Fujiwara ,  Masayoshi Nomura

    IPC: G01R31/3187 ,  G01R31/317 ,  G11C29/02 ,  G01R31/30

    CPC classification number: G01R31/31715 ,  G01R31/3004 ,  G01R31/31717 ,  G11C29/02 ,  G11C29/022 ,  G11C29/1201 ,  G11C29/56 ,  G11C2029/5006

    Abstract: Apparatus and methods provide built-in testing enhancements in integrated circuits. These testing enhancements permit, for example, continuity testing to pads and/or leakage current testing for more than one pad. The disclosed techniques may permit more thorough testing of integrated circuits at the die level, thereby reducing the number of defective devices that are further processed, saving both time and money. In one embodiment, a test signal is routed in real time through a built-in path that includes an input buffer for a pad under test. This permits testing of continuity between the pad and the input buffer. An output buffer can also be tested as applicable. In another embodiment, two or more pads of a die are electronically coupled together such that leakage current testing applied by a probe connected to one pad can be used to test another pad.

    Abstract translation: 装置和方法在集成电路中提供内置的测试增强功能。 这些测试增强允许例如对多于一个焊盘的焊盘和/或泄漏电流测试的连续性测试。 所公开的技术可以允许在芯片级别对集成电路进行更彻底的测试，从而减少进一步处理的缺陷设备的数量，从而节省时间和金钱。 在一个实施例中，测试信号通过内置路径实时路由，该内置路径包括用于待测焊盘的输入缓冲器。 这允许测试焊盘和输入缓冲器之间的连续性。 输出缓冲区也可以根据需要进行测试。 在另一个实施例中，管芯的两个或更多焊盘电耦合在一起，使得由连接到一个焊盘的探头施加的泄漏电流测试可用于测试另一焊盘。

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