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71.发明申请公开(公告)号：US20050243624A1
公开(公告)日：2005-11-03
申请号：US11019188
申请日：2004-12-23
申请人： Ji-Eun Jang
发明人： Ji-Eun Jang
CPC分类号： G11C29/14 , G11C7/08 , G11C2207/065
摘要： A semiconductor memory device capable of controlling a drivability of an overdriver is provided. The semiconductor memory device includes: a first power supply for supplying a normal driving voltage; a memory cell array block; a bit line sense amplifier block for sensing and amplifying voltage difference between bit line pair of the memory cell array block; a first driver for driving a power supply line of the bit line sense amplifier block to a voltage of a node connected with the first power supply in response to a driving control signal; a plurality of second drivers for driving the node to an overdriving voltage higher than the normal driving voltage; and an overdriving drivability controller for selectively activating the second drivers in response to a test-mode drivability control signal inputted during an activation period of an overdriving signal.
摘要翻译： 提供能够控制起动器的驾驶性的半导体存储器件。 半导体存储器件包括：用于提供正常驱动电压的第一电源; 存储单元阵列块; 位线读出放大器块，用于感测和放大存储单元阵列块的位线对之间的电压差; 用于响应于驱动控制信号将位线读出放大器块的电源线驱动到与第一电源连接的节点的电压的第一驱动器; 用于将所述节点驱动到高于所述正常驱动电压的过驱动电压的多个第二驱动器; 以及过驱动驾驶员控制器，用于响应于在过驱动信号的激活期间期间输入的测试模式驾驶性能控制信号选择性地激活第二驾驶员。
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公开(公告)号：US06940774B2
公开(公告)日：2005-09-06
申请号：US10699231
申请日：2003-10-31
申请人： Martin Perner
发明人： Martin Perner
摘要： An integrated dynamic memory includes a memory cell array having memory cells for storing a charge corresponding to an information bit. The memory cell array has a regular cell area with regular memory cells, a first test cell area with first test cells and a second test cell area with second test cells. A control unit is provided for refreshing the charge contents of the regular memory cells with a first refresh time, a control unit is provided for refreshing the charge contents of the first test cells with a second refresh time, and the charge contents of the second test cells with a third refresh time. The first refresh time is shorter than the second refresh time and the latter is shorter than the third refresh time. An evaluation unit is provided for detecting memory cell defects in the first and second test cell areas.
摘要翻译： 集成动态存储器包括具有用于存储对应于信息位的电荷的存储单元的存储单元阵列。 存储单元阵列具有规则的存储单元的单元区域，具有第一测试单元的第一测试单元区域和具有第二测试单元的第二测试单元区域。 提供控制单元，用于在第一刷新时间内刷新常规存储单元的费用内容，提供控制单元，用于刷新具有第二刷新时间的第一测试单元的费用内容，第二测试的费用内容 细胞具有第三次刷新时间。 第一刷新时间比第二刷新时间短，后者比第三刷新时间短。 提供用于检测第一和第二测试单元区域中的存储单元缺陷的评估单元。
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公开(公告)号：US20050193253A1
公开(公告)日：2005-09-01
申请号：US10708184
申请日：2004-02-13
申请人： Jonathan Fales , Gregory Fredeman , Kevin Gorman , Mark Jacunski , Toshiaki Kirihata , Alan Norris , Paul Parries , Matthew Wordeman
发明人： Jonathan Fales , Gregory Fredeman , Kevin Gorman , Mark Jacunski , Toshiaki Kirihata , Alan Norris , Paul Parries , Matthew Wordeman
CPC分类号： G11C29/16 , G11C29/12015 , G11C29/14 , G11C2029/0401
摘要： Disclosed is a flexible command multiplication scheme for the built-in-self test (BIST) of a high-speed embedded memory array that segments BIST functionality into remote lower-speed executable instructions and local higher-speed executable instructions. A stand-alone BIST logic controller operates at a lower frequency and communicates with a command multiplier using a low-speed BIST instruction seed set. The command multiplier uses offset or directive registers to drive a logic unit or ALU to generate “n” sets of CAD information which are then time-multiplexed to the embedded memory at a speed “n” times faster than the BIST operating speed.
摘要翻译： 公开了用于高速嵌入式存储器阵列的内置自检（BIST）的灵活的命令乘法方案，其将BIST功能分段成远程低速可执行指令和本地较高速可执行指令。 独立的BIST逻辑控制器以较低的频率工作，并与使用低速BIST指令种子集的命令乘法器进行通信。 命令乘法器使用偏移或指令寄存器来驱动逻辑单元或ALU以产生“n”组CAD信息，然后以比BIST操作速度快n倍的速度将时间复用到嵌入式存储器。
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公开(公告)号：US20050172194A1
公开(公告)日：2005-08-04
申请号：US10707971
申请日：2004-01-29
申请人： Jeffrey Dreibelbis , Kevin Gorman , Michael Nelms
发明人： Jeffrey Dreibelbis , Kevin Gorman , Michael Nelms
CPC分类号： G11C29/14 , G01R31/31724 , G01R31/3187 , G11C29/16 , G11C29/44 , G11C29/4401 , G11C29/72 , G11C2029/0401
摘要： Disclosed is a hybrid built-in self test (BIST) architecture for embedded memory arrays that segments BIST functionality into remote lower-speed executable instructions and local higher-speed executable instructions. A standalone BIST logic controller operates at a lower frequency and communicates with a plurality of embedded memory arrays using a BIST instruction set. A block of higher-speed test logic is incorporated into each embedded memory array under test and locally processes BIST instructions received from the standalone BIST logic controller at a higher frequency. The higher-speed test logic includes a multiplier for increasing the frequency of the BIST instructions from the lower frequency to the higher frequency. The standalone BIST logic controller enables a plurality of higher-speed test logic structures in a plurality of embedded memory arrays.
摘要翻译： 公开了一种用于嵌入式存储器阵列的混合内置自测（BIST）架构，其将BIST功能分段成远程低速可执行指令和本地较高速可执行指令。 独立的BIST逻辑控制器以较低的频率工作，并使用BIST指令集与多个嵌入式存储器阵列进行通信。 一个高速测试逻辑块被并入被测试的每个嵌入式存储器阵列中，并以更高的频率在本地处理从独立BIST逻辑控制器接收的BIST指令。 高速测试逻辑包括用于将BIST指令的频率从较低频率增加到较高频率的乘法器。 独立的BIST逻辑控制器使多个嵌入式存储器阵列中的多个更高速的测试逻辑结构能够实现。
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75.发明申请公开(公告)号：US20050066247A1
公开(公告)日：2005-03-24
申请号：US10985539
申请日：2004-11-09
申请人： Wu-Tung Cheng , Christopher Hill , Omar Kebichi
发明人： Wu-Tung Cheng , Christopher Hill , Omar Kebichi
摘要： A test circuit is disclosed for testing embedded synchronous memories. A BIST controller is used to address the memory and provide reference data that is compared to the memory output. Pipeline registers are used to allow the BIST controller to perform reads and/or writes during every clock cycle. In one aspect, the BIST controller includes a reference data circuit that stores or generates data for comparison to the memory output. A pipeline register is positioned before the reference data circuit or between the reference data circuit and compare circuitry. Additional pipeline registers may be positioned between a compare capture circuit and the compare circuitry. The pipeline registers free the BIST controller from having to wait for a read to complete before starting the next read or write. To reduce the number of pipeline registers needed, a negative-edge BIST controller can be used with a positive-edge memory or vice versa.
摘要翻译： 公开了一种用于测试嵌入式同步存储器的测试电路。 BIST控制器用于寻址存储器并提供与存储器输出进行比较的参考数据。 流水线寄存器用于允许BIST控制器在每个时钟周期内执行读取和/或写操作。 在一个方面，BIST控制器包括参考数据电路，其存储或产生用于与存储器输出进行比较的数据。 流水线寄存器位于参考数据电路之前或参考数据电路和比较电路之间。 另外的流水线寄存器可以位于比较捕捉电路和比较电路之间。 流水线注册使得BIST控制器在开始下一次读取或写入之前不必等待读取完成。 为了减少所需的流水线寄存器数量，负边缘BIST控制器可以与正边沿存储器一起使用，反之亦然。
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公开(公告)号：US06865707B2
公开(公告)日：2005-03-08
申请号：US10109657
申请日：2002-04-01
申请人： Wolfgang Ernst , Gunnar Krause , Justus Kuhn , Jens Luepke , Jochen Mueller , Peter Poechmueller , Michael Schittenhelm
发明人： Wolfgang Ernst , Gunnar Krause , Justus Kuhn , Jens Luepke , Jochen Mueller , Peter Poechmueller , Michael Schittenhelm
IPC分类号： G01R31/3183 , G11C29/14 , G11C29/36 , G01R31/28 , G06F11/00
CPC分类号： G11C29/14 , G01R31/3183 , G11C29/36
摘要： Test data generator for generating test data patterns for the testing of a circuit having a frequency multiplication circuit, which increases a low clock frequency of an input clock signal received by a test unit with a specific clock frequency multiplication factor. Also provided is a plurality of data registers for storing test data words read from the data registers, and multiplexer that switches through a test data word read from a data register with the high clock frequency of the output clock signal to a data bus in a way dependent on a register selection control datum of a multi-position register selection control data vector.
摘要翻译： 用于产生用于测试具有倍频电路的电路的测试数据模式的测试数据发生器，其增加由测试单元以特定时钟倍频因子接收的输入时钟信号的低时钟频率。 还提供了多个数据寄存器，用于存储从数据寄存器读取的测试数据字，以及多路复用器，以一种方式将通过从输出时钟信号的高时钟频率从数据寄存器读取的测试数据字切换到数据总线 取决于多位置寄存器选择控制数据向量的寄存器选择控制基准。
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公开(公告)号：US06865694B2
公开(公告)日：2005-03-08
申请号：US10136818
申请日：2002-04-30
CPC分类号： G11C29/56 , G11C29/14 , G11C29/16 , G11C29/44 , G11C29/56012 , G11C2029/0401
摘要： A CPU-based system 10 and method for testing embedded memory. The technique employs the on-chip CPU 20 itself to test the embedded memory 24. An assembly code program is loaded into the device under test (DUT) 12 to test the memories, determine a repair solution, and write out the repair solution and raw failure information to the tester for defect analysis. The test is driven by an external programmable clock that is provided by the tester to allow the DUT 12 to run up to its maximum input clock rate in order to maximize throughput. The test is not dependent on the pattern rate of the tester.
摘要翻译： 基于CPU的系统10和用于测试嵌入式存储器的方法。 该技术采用片上CPU20本身来测试嵌入式存储器24.组装代码程序被加载到被测器件（DUT）12中以测试存储器，确定修复解决方案，并写出修复解决方案和原始 故障信息给测试仪进行缺陷分析。 测试由测试仪提供的外部可编程时钟驱动，以允许DUT 12运行到其最大输入时钟速率，以最大化吞吐量。 测试不依赖于测试仪的模式速率。
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公开(公告)号：US06853595B2
公开(公告)日：2005-02-08
申请号：US10284174
申请日：2002-10-31
IPC分类号： G11C11/408 , G11C11/401 , G11C29/12 , G11C29/14 , G11C11/00
摘要： A semiconductor memory device having a plurality of pair cells including a pair of cells for storing ordinary data and auxiliary data in which the operation of one cell in a pair cell can be checked. At normal operation time data can be read from or written to a desired cell by activating two word lines at a time. On the other hand, at operation test time data can be read from or written to only one cell in a pair cell by activating a desired word line.
摘要翻译： 一种半导体存储器件，具有包括一对用于存储普通数据的单元的多个单元，以及可以检查一对单元中的一个单元的操作的辅助数据。 在正常操作时，可以通过同时激活两条字线来读取或写入所需单元格。 另一方面，在操作测试时，通过激活所需字线，数据可以从一个单元中的一个单元读取或写入其中。
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公开(公告)号：US20050007172A1
公开(公告)日：2005-01-13
申请号：US10886672
申请日：2004-07-09
CPC分类号： G11C29/14 , G11C29/46 , G11C2029/0405 , G11C2029/2602
摘要： Conventionally, when a burn-in test is performed by means of utilizing a memory BIST circuit, a control of a reset operation for the memory BIST circuit is required from an external source. According to the present invention, it is configured that the memory BIST circuit is used for the burn-in test of a memory macro, and a BIST reset control circuit detects a memory BIST test completion signal from the memory BIST circuit, and automatically resets the memory BIST circuit. Thereby, repetitive continuous tests to the memory macro by the memory BIST circuit can be achieved, and the burn-in test by means of utilizing the memory BIST circuit can be performed.
摘要翻译： 通常，当通过利用存储器BIST电路进行老化测试时，需要从外部源控制存储器BIST电路的复位操作。 根据本发明，存储器BIST电路用于存储器宏的老化测试，BIST复位控制电路从存储器BIST电路检测存储器BIST测试完成信号，并自动复位 内存BIST电路。 因此，可以实现由存储器BIST电路对存储器宏的重复连续测试，并且可以执行利用存储器BIST电路的老化测试。
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公开(公告)号：US06842398B2
公开(公告)日：2005-01-11
申请号：US10703275
申请日：2003-11-07
IPC分类号： G01R31/28 , G11C7/10 , G11C7/22 , G11C11/401 , G11C11/407 , G11C29/14 , G11C8/00
CPC分类号： G11C29/12015 , G11C7/1078 , G11C7/109 , G11C7/22 , G11C7/222 , G11C29/14
摘要： A synchronous semiconductor memory device is operable in a normal mode and an alternative mode. The semiconductor device has a command bus for receiving a plurality of synchronously captured input signals, and a plurality of asynchronous input terminals for receiving a plurality of asynchronous input signals. The device further has a clock input for receiving an external clock signal thereon, with the device being specified by the manufacturer to be operated in the normal mode using an external clock signal having a frequency no less than a predetermined minimum frequency. An internal delay locked loop (DLL) clocking circuit is coupled to the clock input terminal and is responsive in normal operating mode to be responsive to the external clock signal to generate at least one internal clock signal. control circuitry in the device is responsive to a predetermined sequence of asynchronous signals applied to the device's asynchronous input terminals to place the device in an alternative mode of operation in which the internal clocking circuit is disabled, such that the device may be operated in the alternative mode using an external clock signal having a frequency less than the predetermined minimum frequency. The alternative mode of operation facilitates testing of the device at a speed less than the minimum frequency specified for the normal mode of operation.
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