INFORMATION PROCESSING SYSTEM, INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD AND COMPUTER READABLE MEDIUM
    2.
    发明申请
    INFORMATION PROCESSING SYSTEM, INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD AND COMPUTER READABLE MEDIUM 有权
    信息处理系统,信息处理装置,信息处理方法和计算机可读介质

    公开(公告)号:US20100191751A1

    公开(公告)日:2010-07-29

    申请号:US12548394

    申请日:2009-08-26

    申请人: Shoji Sakamoto

    发明人: Shoji Sakamoto

    IPC分类号: G06F17/30

    CPC分类号: G06F17/30176

    摘要: An information processing system includes an acceptance section, a first processing section, a conversion section and a second processing section. The acceptance section accepts first storage location information that is indicative of where a first electronic file in a first storage unit is stored. The first processing section processes the first electronic file in accordance with a first processing content. The conversion section converts the first storage location information to second storage location information that is indicative of where a second electronic file in a second storage unit is stored. The second electronic file has an identical content as that of the first electronic file. The second processing section processes the second electronic file in accordance with a second processing content.

    摘要翻译: 信息处理系统包括接收部分,第一处理部分,转换部分和第二处理部分。 接收部接受表示第一存储单元中的第一电子文件在哪里被存储的第一存储位置信息。 第一处理部根据第一处理内容处理第一电子文件。 转换部分将第一存储位置信息转换为指示存储第二存储单元中的第二电子文件的位置的第二存储位置信息。 第二电子文件具有与第一电子文件相同的内容。 第二处理部分根据第二处理内容处理第二电子文件。

    Semiconductor integrated circuit device
    3.
    发明申请
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号:US20050007172A1

    公开(公告)日:2005-01-13

    申请号:US10886672

    申请日:2004-07-09

    摘要: Conventionally, when a burn-in test is performed by means of utilizing a memory BIST circuit, a control of a reset operation for the memory BIST circuit is required from an external source. According to the present invention, it is configured that the memory BIST circuit is used for the burn-in test of a memory macro, and a BIST reset control circuit detects a memory BIST test completion signal from the memory BIST circuit, and automatically resets the memory BIST circuit. Thereby, repetitive continuous tests to the memory macro by the memory BIST circuit can be achieved, and the burn-in test by means of utilizing the memory BIST circuit can be performed.

    摘要翻译: 通常,当通过利用存储器BIST电路进行老化测试时,需要从外部源控制存储器BIST电路的复位操作。 根据本发明,存储器BIST电路用于存储器宏的老化测试,BIST复位控制电路从存储器BIST电路检测存储器BIST测试完成信号,并自动复位 内存BIST电路。 因此,可以实现由存储器BIST电路对存储器宏的重复连续测试,并且可以执行利用存储器BIST电路的老化测试。

    Information processing system, information processing apparatus, information processing method and computer readable medium
    6.
    发明授权
    Information processing system, information processing apparatus, information processing method and computer readable medium 有权
    信息处理系统,信息处理装置,信息处理方法和计算机可读介质

    公开(公告)号:US08346786B2

    公开(公告)日:2013-01-01

    申请号:US12548394

    申请日:2009-08-26

    申请人: Shoji Sakamoto

    发明人: Shoji Sakamoto

    IPC分类号: G06F17/30

    CPC分类号: G06F17/30176

    摘要: An information processing system includes an acceptance section, a first processing section, a conversion section and a second processing section. The acceptance section accepts first storage location information that is indicative of where a first electronic file in a first storage unit is stored. The first processing section processes the first electronic file in accordance with a first processing content. The conversion section converts the first storage location information to second storage location information that is indicative of where a second electronic file in a second storage unit is stored. The second electronic file has an identical content as that of the first electronic file. The second processing section processes the second electronic file in accordance with a second processing content.

    摘要翻译: 信息处理系统包括接收部分,第一处理部分,转换部分和第二处理部分。 接收部接受表示第一存储单元中的第一电子文件在哪里被存储的第一存储位置信息。 第一处理部根据第一处理内容处理第一电子文件。 转换部分将第一存储位置信息转换为指示存储第二存储单元中的第二电子文件的位置的第二存储位置信息。 第二电子文件具有与第一电子文件相同的内容。 第二处理部分根据第二处理内容处理第二电子文件。

    INFORMATION SHARING SUPPORT SYSTEM, INFORMATION PROCESSING DEVICE, COMPUTER READABLE RECORDING MEDIUM, AND COMPUTER CONTROLLING METHOD
    7.
    发明申请
    INFORMATION SHARING SUPPORT SYSTEM, INFORMATION PROCESSING DEVICE, COMPUTER READABLE RECORDING MEDIUM, AND COMPUTER CONTROLLING METHOD 审中-公开
    信息共享支持系统,信息处理设备,计算机可读记录介质和计算机控制方法

    公开(公告)号:US20120324330A1

    公开(公告)日:2012-12-20

    申请号:US13529760

    申请日:2012-06-21

    IPC分类号: G06F17/00

    摘要: An information sharing support system includes a first information processor connected to a projector that projects an image on a projection area including an object, and to an image pick-up device for picking up an image of the projection area; an inputting unit that inputs an event in a first layer, inputs a second annotation image as a part of a first annotation image associated with the event to a second layer, inputs a third annotation image to a third layer, and inputs a document to a fourth layer; a transmitter that transmits the second annotation image to the projector device; a receiving unit that receives a picked-up image; and a second information processing device that allocates the picked-up image to the second layer, and includes a display that displays the third annotation image and the document in an overlapping fashion.

    摘要翻译: 信息共享支持系统包括连接到投影仪的第一信息处理器,投影仪在包括对象的投影区域上投影图像,并且包括用于拾取投影区域的图像的图像拾取装置; 输入单元,其输入第一层中的事件,将作为与所述事件相关联的第一注释图像的一部分的第二注释图像输入到第二层,将第三注释图像输入到第三层,并将文档输入到 第四层 将所述第二注释图像发送到所述投影仪装置的发射器; 接收单元,其接收拾取图像; 以及第二信息处理设备,其将拾取的图像分配给第二层,并且包括以重叠的方式显示第三注释图像和文档的显示器。

    PHOTOGRAPHING APPARATUS AND PHOTOGRAPHING SYSTEM
    8.
    发明申请
    PHOTOGRAPHING APPARATUS AND PHOTOGRAPHING SYSTEM 有权
    摄影装置和摄影系统

    公开(公告)号:US20100066865A1

    公开(公告)日:2010-03-18

    申请号:US12411931

    申请日:2009-03-26

    申请人: Shoji SAKAMOTO

    发明人: Shoji SAKAMOTO

    IPC分类号: H04N5/262

    摘要: Provided is a photographing apparatus that includes a photographing section that photographs a subject, and a controller that controls a photographing range of the photographing section based on a range specification image that is projected onto the subject.

    摘要翻译: 本发明提供一种拍摄设备,其包括拍摄对象的拍摄部分,以及基于投影到被摄体上的范围指定图像来控制拍摄部分的拍摄范围的控制器。

    Semiconductor device having integrated memory and logic
    9.
    发明授权
    Semiconductor device having integrated memory and logic 失效
    具有集成存储器和逻辑的半导体器件

    公开(公告)号:US06785187B2

    公开(公告)日:2004-08-31

    申请号:US10325932

    申请日:2002-12-23

    IPC分类号: G11C800

    摘要: In a conventional DRAM, row addresses and column addresses are latched by DFF and decoding of addresses is started a certain time after a clock rise, and it takes a long time after the clock rise until the decoding is completed, having a problem that it is not possible to perform read/write at high speed. The present invention adopts a configuration connecting latch circuits such as the row address latch circuits and column address latch circuits using a scan chain. This makes decoding of row addresses and column addresses start when the clock is “L”, making it possible to complete decoding on the rise of each operation clock cycle, shorten the operation clock cycle and speed up read/write. The conventional art conducts a test on the connection between the row addresses and column addresses of the logic section and memory through an actual operation test of the entire LSI, resulting in a low circuit failure detection rate. The present invention conducts this test through a scan test, making it possible to automatically create test patterns with high circuit failure detection rate.

    摘要翻译: 在常规DRAM中,行地址和列地址被DFF锁存,地址的解码在时钟上升之后的特定时间开始,并且在时钟上升直到解码完成之后需要很长时间,具有这样的问题 不可能高速执行读/写。 本发明采用使用扫描链连接诸如行地址锁存电路和列地址锁存电路的锁存电路的配置。 这使得当时钟为“L”时,行地址和列地址的解码开始,使得可以在每个操作时钟周期的上升完成解码,缩短操作时钟周期并加快读/写速度。 传统技术通过整个LSI的实际操作测试来对逻辑部分和存储器的行地址和列地址之间的连接进行测试,导致低电路故障检测率。 本发明通过扫描测试进行该测试,使得可以自动创建具有高电路故障检测速率的测试图案。

    Image forming apparatus and method of generating gradation pattern
    10.
    发明授权
    Image forming apparatus and method of generating gradation pattern 失效
    图像形成装置和产生渐变图案的方法

    公开(公告)号:US06201550B1

    公开(公告)日:2001-03-13

    申请号:US09106136

    申请日:1998-06-29

    申请人: Shoji Sakamoto

    发明人: Shoji Sakamoto

    IPC分类号: G06K900

    CPC分类号: G06T11/001

    摘要: A high-speed image forming apparatus may alleviate a load imposed upon the drawing processing of the gradation. A drawing unit writes data in a page buffer while executing the drawing processing by using the drawing data stored in a drawing data storage unit. At that time, when generation of the gradation is instructed, the drawing unit accesses a gradation generation unit. The gradation generation unit sets a plurality of adjacent band-like regions which are perpendicular to a straight line connecting a start point with an end point and in which color values therein become uniform by using the vector of the changing direction of the transferred color and the color information at the start and endpoints, obtains the intersection point between the boundary of the band-like region and the scanning line, and sets such intersection point as the color changing point. At every scanning line, the color changing point and the color between the color changing points are successively obtained, and the gradation pattern in the scanning direction is generated successively.

    摘要翻译: 高速图像形成装置可以减轻对渐变的绘制处理施加的负荷。 绘图单元通过使用存储在绘图数据存储单元中的绘图数据执行绘图处理,将数据写入页缓冲器。 此时,当指示灰度的生成时,绘图单元访问灰度生成单元。 灰度生成单元通过使用所转印颜色的变化方向的向量,设置与连接起始点与终点的直线垂直的多个相邻的带状区域,并且其中的颜色值变得均匀, 在开始和结束点处的颜色信息,获得带状区域和扫描线的边界之间的交点,并将这样的交点设置为颜色变化点。 在每个扫描线上,依次获得颜色变化点和颜色变化点之间的颜色,并连续地生成扫描方向上的渐变图案。