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    Active termination circuit and method for controlling the impedance of external integrated circuit terminals
    3.
    发明授权
    Active termination circuit and method for controlling the impedance of external integrated circuit terminals 有权
    有源终端电路及控制外部集成电路端子阻抗的方法

    公开(公告)号：US08054703B2

    公开(公告)日：2011-11-08

    申请号：US12760841

    申请日：2010-04-15

    申请人： Chris G. Martin

    发明人： Chris G. Martin

    IPC分类号： G11C7/00

    CPC分类号： G11C7/1084 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1072 ,  G11C7/1078 ,  G11C11/4093 ,  G11C2207/105 ,  G11C2207/2254

    摘要： An active termination circuit is used to set the input impedance of a plurality of input terminals. Each of the input terminals is coupled to a supply voltage through at least one PMOS transistor and to ground through at least one NMOS transistor. The impedances of the transistors are controlled by a control circuit that generates a first control signal to set the impedance of another PMOS transistor to be equal to a first predetermined resistance, and generates a second control signal to set the impedance of another NMOS transistor to be equal to a second predetermined resistance. The first control signal is used to control all of the PMOS transistors and the second control signal is used to control all of the NMOS transistors. As a result, the PMOS and NMOS transistors coupled to each input terminal have impedances corresponding to the first and second resistances, respectively.

    摘要翻译： 使用有源终端电路来设定多个输入端子的输入阻抗。 每个输入端通过至少一个PMOS晶体管耦合到电源电压，并通过至少一个NMOS晶体管接地。 晶体管的阻抗由产生第一控制信号以将另一PMOS晶体管的阻抗设置为等于第一预定电阻的控制电路来控制，并产生第二控制信号以将另一个NMOS晶体管的阻抗设置为 等于第二预定电阻。 第一控制信号用于控制所有PMOS晶体管，第二控制信号用于控制所有NMOS晶体管。 结果，耦合到每个输入端的PMOS和NMOS晶体管分别具有对应于第一和第二电阻的阻抗。

    Multi-mode synchronous memory device and methods of operating and testing same
    5.
    发明授权
    Multi-mode synchronous memory device and methods of operating and testing same 失效
    多模同步存储器件及其操作和测试方法相同

    公开(公告)号：US07057967B2

    公开(公告)日：2006-06-06

    申请号：US11001231

    申请日：2004-12-01

    申请人： Brian Johnson ,  Brent Keeth ,  Jeffrey W. Janzen ,  Troy A. Manning ,  Chris G. Martin

    发明人： Brian Johnson ,  Brent Keeth ,  Jeffrey W. Janzen ,  Troy A. Manning ,  Chris G. Martin

    IPC分类号： G11C8/00

    CPC分类号： G11C29/12015 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/22 ,  G11C7/222 ,  G11C29/14

    摘要： A synchronous semiconductor memory device is operable in a normal mode and an alternative mode. The semiconductor device has a command bus for receiving a plurality of synchronously captured input signals, and a plurality of asynchronous input terminals for receiving a plurality of asynchronous input signals. The device further has a clock input for receiving an external clock signal thereon, with the device being specified by the manufacturer to be operated in the normal mode using an external clock signal having a frequency no less than a predetermined minimum frequency. An internal delay locked loop (DLL) clocking circuit is coupled to the clock input terminal and is responsive in normal operating mode to be responsive to the external clock signal to generate at least one internal clock signal. control circuitry in the device is responsive to a predetermined sequence of asynchronous signals applied to the device's asynchronous input terminals to place the device in an alternative mode of operation in which the internal clocking circuit is disabled, such that the device may be operated in the alternative mode using an external clock signal having a frequency less than the predetermined minimum frequency. The alternative mode of operation facilitates testing of the device at a speed less than the minimum frequency specified for the normal mode of operation.

    摘要翻译： 同步半导体存储器件可以在正常模式和替代模式下操作。 半导体器件具有用于接收多个同步捕获的输入信号的命令总线和用于接收多个异步输入信号的多个异步输入端子。 该装置还具有用于在其上接收外部时钟信号的时钟输入，该装置由制造商指定为使用具有不小于预定最小频率的频率的外部时钟信号在正常模式下操作。 内部延迟锁定环（DLL）时钟电路耦合到时钟输入端并且在正常操作模式下响应于外部时钟信号响应以产生至少一个内部时钟信号。 设备中的控制电路响应于施加到设备的异步输入端子的预定的异步信号序列，以将设备置于其中内部时钟电路被禁用的替代操作模式，使得该设备可以以替代方式操作 模式使用具有小于预定最小频率的频率的外部时钟信号。 替代的操作模式便于以低于为正常操作模式指定的最小频率的速度测试设备。

    Method and system for selecting redundant rows and columns of memory cells
    6.
    发明授权
    Method and system for selecting redundant rows and columns of memory cells 失效
    用于选择存储单元的冗余行和列的方法和系统

    公开(公告)号：US07054207B2

    公开(公告)日：2006-05-30

    申请号：US10966746

    申请日：2004-10-15

    申请人： Brent Keeth ,  Troy A. Manning ,  Chris G. Martin ,  Ebrahim H. Hargan

    发明人： Brent Keeth ,  Troy A. Manning ,  Chris G. Martin ,  Ebrahim H. Hargan

    IPC分类号： G11C7/00

    CPC分类号： G11C29/848

    摘要： A system and method for selecting redundant rows and columns of memory devices includes a column select steering circuit to couple column select signals from a column address decoder to an array of memory cells. The system and method also includes a fuse banks for programming respective addresses of up to two defective columns that are to be repaired. The programmed addresses are applied to a defective column decoder that determines which column select signal(s) should be shifted downwardly and which column select signal(s) should be shifted upwardly. The column select steering circuit responds to signals from the defective column decoder to shift the column select signals downwardly or upwardly. The column select signal for the lowest column is shifted downwardly to a redundant column, and the column select signal for the highest column is shifted upwardly to a redundant column.

    摘要翻译： 用于选择存储器件的冗余行和列的系统和方法包括：列选择转向电路，用于将列选择信号从列地址解码器耦合到存储器单元阵列。 该系统和方法还包括用于编程待修复的多达两个缺陷列的相应地址的熔丝组。 编程的地址被应用于有缺陷的列解码器，该解码器确定哪个列选择信号应该被向下移位，哪个列选择信号应向上移位。 列选择转向电路响应来自故障列解码器的信号，以向下或向上移动列选择信号。 最低列的列选择信号向下移动到冗余列，最高列的列选择信号向上移动到冗余列。

    Active termination circuit and method for controlling the impedance of external integrated circuit terminals
    7.
    发明授权
    Active termination circuit and method for controlling the impedance of external integrated circuit terminals 失效

    公开(公告)号：US06711073B2

    公开(公告)日：2004-03-23

    申请号：US10375639

    申请日：2003-02-26

    申请人： Chris G. Martin

    发明人： Chris G. Martin

    IPC分类号： G06F1300

    CPC分类号： G11C7/1084 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1072 ,  G11C7/1078 ,  G11C11/4093 ,  G11C2207/105 ,  G11C2207/2254

    摘要： An active termination circuit is used to set the input impedance of a plurality of input terminals. Each of the input terminals is coupled to a supply voltage through at least one PMOS transistor and to ground through at least one NMOS transistor. The impedances of the transistors are controlled by a control circuit that generates a first control signal to set the impedance of another PMOS transistor to be equal to a first predetermined resistance, and generates a second control signal to set the impedance of another NMOS transistor to be equal to a second predetermined resistance. The first control signal is used to control all of the PMOS transistors and the second control signal is used to control all of the NMOS transistors. As a result, the PMOS and NMOS transistors coupled to each input terminal have impedances corresponding to the first and second resistances, respectively.

    Active termination circuit and method for controlling the impedance of external integrated circuit terminals
    8.
    发明授权
    Active termination circuit and method for controlling the impedance of external integrated circuit terminals 失效
    有源终端电路及控制外部集成电路端子阻抗的方法

    公开(公告)号：US06657906B2

    公开(公告)日：2003-12-02

    申请号：US09997156

    申请日：2001-11-28

    申请人： Chris G. Martin

    发明人： Chris G. Martin

    IPC分类号： G11C700

    CPC分类号： G11C7/1084 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1072 ,  G11C7/1078 ,  G11C11/4093 ,  G11C2207/105 ,  G11C2207/2254

    摘要： An active termination circuit is used to set the input impedance of a plurality of input terminals. Each of the input terminals is coupled to a supply voltage through at least one PMOS transistor and to ground through at least one NMOS transistor. The impedances of the transistors are controlled by a control circuit that generates a first control signal to set the impedance of another PMOS transistor to be equal to a first predetermined resistance, and generates a second control signal to set the impedance of another NMOS transistor to be equal to a second predetermined resistance. The first control signal is used to control all of the PMOS transistors and the second control signal is used to control all of the NMOS transistors. As a result, the PMOS and NMOS transistors coupled to each input terminal have impedances corresponding to the first and second resistances, respectively.

    摘要翻译： 使用有源终端电路来设定多个输入端子的输入阻抗。 每个输入端通过至少一个PMOS晶体管耦合到电源电压，并通过至少一个NMOS晶体管接地。 晶体管的阻抗由产生第一控制信号以将另一PMOS晶体管的阻抗设置为等于第一预定电阻的控制电路来控制，并产生第二控制信号以将另一NMOS晶体管的阻抗设置为 等于第二预定电阻。 第一控制信号用于控制所有PMOS晶体管，第二控制信号用于控制所有NMOS晶体管。 结果，耦合到每个输入端的PMOS和NMOS晶体管分别具有对应于第一和第二电阻的阻抗。

    Antifuse detection circuit
    9.
    发明授权
    Antifuse detection circuit 有权
    防腐检测电路

    公开(公告)号：US06633506B2

    公开(公告)日：2003-10-14

    申请号：US09771818

    申请日：2001-01-29

    申请人： Stephen L. Casper ,  Chris G. Martin

    发明人： Stephen L. Casper ,  Chris G. Martin

    IPC分类号： G11C1140

    CPC分类号： G11C17/18

    摘要： An antifuse detection circuit is described which uses a latching circuit and two antifuses. The antifuses are coupled between the latch circuit and ground. The latching circuit described is a differential circuit which can detect which one of the two antifuses has been programmed. The circuit accurately detects an antifuse which has a relatively high resistance after being programmed.

    摘要翻译： 描述了使用锁存电路和两个反熔丝的反熔丝检测电路。 反熔丝耦合在锁存电路和地之间。 所描述的锁存电路是可以检测两个反熔丝中的哪一个已被编程的差分电路。 该电路准确地检测到在编程后具有较高电阻的反熔丝。

    Lead frame decoupling capacitor semiconductor device packages including the same and methods
    10.
    发明授权
    Lead frame decoupling capacitor semiconductor device packages including the same and methods 失效
    引线框架去耦电容器，半导体器件封装包括相同

    公开(公告)号：US06515359B1

    公开(公告)日：2003-02-04

    申请号：US09009668

    申请日：1998-01-20

    申请人： David J. Corisis ,  Chris G. Martin

    发明人： David J. Corisis ,  Chris G. Martin

    IPC分类号： H01L2352

    CPC分类号： H01L23/49589 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01076 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

    摘要： A lead frame assembly including at least two layers. A first of the lead frame layers includes a first wide, electrically conductive bus and a plurality of leads that extend substantially unidirectionally from a single edge of the lead frame assembly. The second lead frame layer includes a second wide, electrically conductive bus that is superimposed over the first bus and a plurality of lead fingers extending substantially unidirectionally from a single edge of the lead frame assembly. Preferably, the lead fingers of both the first and second layers extend in substantially the same direction. An insulator element is disposed between the first and second buses. One of the buses is connectable to a power supply source (Vcc), while the other is connectable to a power supply ground (Vss). Thus, the co-extensive portions of the first and second buses form a decoupling capacitor. Lead fingers which are connected to the power supply source (Vcc) are preferably grouped into at least one group and flank the remainder of the lead fingers so that they are not interleaved therewith. Preferably, upon attachment of the lead frame assembly to a semiconductor device, the decoupling capacitor extends over a substantial portion of the latter.

    摘要翻译： 包括至少两层的引线框架组件。 引线框架层中的第一个包括第一宽导电总线和从引线框架组件的单个边缘基本上单向延伸的多个引线。 第二引线框架层包括叠置在第一总线上的第二宽导电总线，以及从引线框架组件的单个边缘基本上单向地延伸的多个引线指。 优选地，第一和第二层两者的引导指沿基本相同的方向延伸。 绝缘体元件设置在第一和第二母线之间。 其中一条总线可连接到电源（Vcc），另一条可连接到电源地（Vss）。 因此，第一和第二总线的共同扩展部分形成去耦电容器。 连接到电源（Vcc）的引线指针优选地被分组成至少一个组，并且在引线的其余部分的侧面被分组，使得它们不与其交错。 优选地，在将引线框架组件附接到半导体器件上时，去耦电容器延伸在后者的大部分上。