公开(公告)号：US20240276731A1

公开(公告)日：2024-08-15

申请号：US18641654

申请日：2024-04-22

Applicant: SK hynix Inc.

Inventor： Eun Seok CHOI

IPC: H10B43/50 ,  H01L23/535 ,  H10B41/27 ,  H10B41/41 ,  H10B41/50 ,  H10B43/27 ,  H10B43/40 ,  H10B63/00

CPC classification number: H10B43/50 ,  H01L23/535 ,  H10B41/27 ,  H10B41/41 ,  H10B41/50 ,  H10B43/27 ,  H10B43/40 ,  H10B63/34 ,  H10B63/845

Abstract: A semiconductor device includes a stacked body including stacked insulating layers and stacked conductive layers; a cell plug; a connection contact structure; and a source layer coupled to the cell plug. The cell plug includes upper and lower portions, the connection contact structure includes a first connection contact disposed at substantially the same level as the lower portion of the cell plug, and a second connection contact disposed at substantially the same level as the upper portion thereof, a level at which the first and second connection contacts contact each other is substantially the same as a level at which the upper and lower portions of the cell plug contact each other, and a level of an uppermost portion of the second connection contact is higher than a level of a bottom surface of the source layer, and is lower than a level of a top surface thereof.

公开(公告)号：US20240268241A1

公开(公告)日：2024-08-08

申请号：US18105922

申请日：2023-02-06

Applicant: GlobalFoundries Singapore Pte. Ltd.

Inventor： Curtis Chun-I Hsieh ,  Kai Kang ,  Wanbing Yi ,  Yongshun Sun ,  Eng-Huat Toh ,  Juan Boon Tan

IPC: H10N70/00 ,  H01L23/528 ,  H10B63/00

CPC classification number: H10N70/841 ,  H01L23/5283 ,  H10B63/34 ,  H10N70/063 ,  H10N70/883

Abstract: Structures that include a layer stack for a resistive memory element and methods of forming a structure that includes a layer stack for a resistive memory element. The structure comprises a resistive memory element including a first electrode, a second electrode, and a switching layer disposed between the second electrode and the first electrode. The first electrode includes a first layer and a second layer between the first layer and the switching layer. The switching layer has a first thickness, and the second layer of the first electrode has a second thickness that is less than the first thickness of the switching layer.

公开(公告)号：US12010844B2

公开(公告)日：2024-06-11

申请号：US17216093

申请日：2021-03-29

Applicant: SK hynix Inc.

Inventor： Dong Hun Lee ,  Mi Seong Park ,  Jung Shik Jang ,  Jung Dal Choi ,  In Su Park

IPC: H10B43/27 ,  H10B41/27 ,  H10B63/00

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B63/34 ,  H10B63/845

Abstract: A semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device including a stacked body including conductive patterns and insulating patterns that are alternately stacked, a filling layer configured to pass through the stacked body, a first channel layer configured to pass through the stacked body and coupled to the filling layer, a second channel layer configured to pass through the stacked body and coupled to the filling layer, a first interposed layer configured to pass through the stacked body and disposed between the first channel layer and the filling layer, a second interposed layer configured to pass through the stacked body and disposed between the second channel layer and the filling layer, and a memory layer surrounding the filling layer, the first and second channel layers, and the first and second interposed layers.

公开(公告)号：US20240179922A1

公开(公告)日：2024-05-30

申请号：US17782868

申请日：2021-08-06

Applicant: ICLEAGUE TECHNOLOGY CO., LTD.

Inventor： Wenyu HUA ,  Xilong WANG

IPC: H10B63/00 ,  H10B12/00 ,  H10B63/10

CPC classification number: H10B63/34 ,  H10B12/05 ,  H10B12/33 ,  H10B63/10

Abstract: Embodiments provide a transistor and a method for manufacturing same, a semiconductor device and a method for manufacturing same. The method for manufacturing a transistor includes operations. A wafer is provided, the wafer has multiple transistor formation regions, each of which has a transistor pillar with an exposed gate formation surface. A gate oxide layer and a gate are sequentially formed on the gate formation surface of each of the transistor pillars. A source is formed at a first end of each of the transistor pillars. A drain is formed at a second end of each of the transistor pillars, here the first end and the second end are opposite ends of each of the transistor pillars in a first direction which is a thickness direction of the wafer; a part of each of the transistor pillars between the source and the drain forms a channel region of the transistor.

公开(公告)号：US20240164116A1

公开(公告)日：2024-05-16

申请号：US18215280

申请日：2023-06-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngji NOH ,  Jongho WOO ,  Joo-Heon KANG ,  Kyunghoon KIM ,  Myunghun WOO

IPC: H10B63/00

CPC classification number: H10B63/845 ,  H10B63/34

Abstract: A semiconductor device includes a gate stacked structure including gate patterns and insulating patterns that are alternately stacked with each other; a gate insulating layer on a sidewall of the gate stacked structure; a channel layer surrounded by the gate insulating layer; a source line surrounded by the channel layer; a variable resistive layer surrounded by the channel layer; and a drain line surrounded by the channel layer.

公开(公告)号：US20240147739A1

公开(公告)日：2024-05-02

申请号：US18208979

申请日：2023-06-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Hong KIM ,  Tae-Seok JANG ,  Hyun-Mook CHOI

IPC: H10B63/00 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

CPC classification number: H10B63/845 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H10B63/34 ,  H10B80/00 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/1443

Abstract: A semiconductor memory device comprising a peripheral circuit structure and a cell structure stacked on the peripheral circuit structure, wherein the cell structure includes a cell substrate including a first face facing the peripheral circuit structure and a second face opposite the first face, a first mold stack including a plurality of first gate electrodes sequentially stacked on the first face, and a channel hole extending through the plurality of first gate electrodes. A channel structure includes a gate dielectric film, a semiconductor film, and a variable resistance film sequentially stacked in the channel hole, wherein the semiconductor film includes a sidewall portion intersecting the first face and the plurality of first gate electrodes, and a top plate portion extending from the sidewall portion in the cell substrate in a parallel manner to the first face.

公开(公告)号：US20240107903A1

公开(公告)日：2024-03-28

申请号：US18182991

申请日：2023-03-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  NATIONAL TAIWAN UNIVERSITY

Inventor： Shih-Yen LIN ,  Po-Cheng TSAI

IPC: H10N70/00 ,  H10B63/00

CPC classification number: H10N70/882 ,  H10B63/34 ,  H10N70/063

Abstract: A memory device includes a substrate, a 2-D material channel layer, a 2-D material charge storage layer, source/drain contacts, a gate dielectric layer, and a gate electrode. The 2-D material channel layer is over the substrate. The 2-D material charge storage layer is over the 2-D material channel layer. The 2-D charge storage layer and the 2-D material channel layer include the same chalcogen atoms. The source/drain contacts are over the 2-D material channel layer. The gate dielectric layer covers the source/drain contacts and the 2-D material charge storage layer. The gate electrode is over the gate dielectric layer.

公开(公告)号：US11943937B2

公开(公告)日：2024-03-26

申请号：US18171497

申请日：2023-02-20

Applicant: Zeno Semiconductor, Inc.

Inventor： Jin-Woo Han ,  Yuniarto Widjaja

IPC: H10B63/00 ,  H10B41/00 ,  H10B61/00

CPC classification number: H10B63/34 ,  H10B41/00 ,  H10B61/22 ,  H10B63/32 ,  H10B63/84

Abstract: A semiconductor metal-oxide-semiconductor field effect transistor (MOSFET) with increased on-state current obtained through a parasitic bipolar junction transistor (BJT) of the MOSFET. Methods of operating the MOSFET as a memory cell or a memory array select transistor are provided.

公开(公告)号：US11925037B2

公开(公告)日：2024-03-05

申请号：US17804958

申请日：2022-06-01

Applicant: Micron Technology, Inc.

Inventor： Yi Hu

IPC: H10B63/00 ,  H01L21/02 ,  H01L21/768 ,  H01L21/8238 ,  H01L25/065 ,  H10B20/00 ,  H10B41/10 ,  H10B41/27 ,  H10B43/35

CPC classification number: H10B63/84 ,  H01L21/02074 ,  H01L21/76885 ,  H01L21/823885 ,  H01L25/0657 ,  H10B20/40 ,  H10B20/50 ,  H10B41/10 ,  H10B41/27 ,  H10B43/35 ,  H10B63/34

Abstract: Methods for forming microelectronic devices include forming lower and upper stack structures, each comprising vertically alternating sequences of insulative and other structures arranged in tiers. Lower and upper pillar structures are formed to extend through the lower and upper stack structures, respectively. An opening is formed through the upper stack structure, and at least a portion of the other structures of the upper stack are replaced by (e.g., chemically converted into) conductive structures, which may be configured as select gate structures. Subsequently, a slit is formed, extending through both the upper and lower stack structures, and at least a portion of the other structures of the lower stack structure are replaced by a conductive material within a liner to form additional conductive structures, which may be configured as access lines (e.g., word lines). Microelectronic devices and structures and related electronic systems are also disclosed.

公开(公告)号：US20240074190A1

公开(公告)日：2024-02-29

申请号：US18117961

申请日：2023-03-06

Applicant: SK hynix Inc.

Inventor： Jae Taek KIM

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/35 ,  H10B43/40 ,  H10B63/00

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/35 ,  H10B43/40 ,  H10B63/34 ,  H10B63/845

Abstract: A semiconductor device includes a substrate, a source structure disposed on the substrate, and cell stack structures disposed on the source structure. The semiconductor device also includes a dummy stack structure disposed between the cell stack structures on the source structure and vertical barriers disposed between the dummy stack structure and the cell stack structures. The semiconductor device further includes at least one lower protective pattern disposed at a lower portion of the dummy stack structure between the vertical barriers.