公开(公告)号：US3008057A

公开(公告)日：1961-11-07

申请号：US76715158

申请日：1958-10-14

Applicant: BURROUGHS CORP

Inventor： CAMPBELL JR CARL M

IPC: H03K3/011 ,  H03K3/281 ,  H03K19/12 ,  H03L1/02

CPC classification number: H03L1/02 ,  H03K3/011 ,  H03K3/281 ,  H03K19/12

公开(公告)号：US2407360A

公开(公告)日：1946-09-10

申请号：US50637743

申请日：1943-10-15

Applicant: ALEX THOMSON

Inventor： WHITE SIDNEY Y

IPC: H03L1/02

CPC classification number: H03L1/02

公开(公告)号：US2280527A

公开(公告)日：1942-04-21

申请号：US35571440

申请日：1940-09-07

Applicant: RCA CORP

Inventor： KIMBALL CHARLES N

IPC: H03L1/02

CPC classification number: H03L1/02

公开(公告)号：US2230216A

公开(公告)日：1941-01-28

申请号：US19093738

申请日：1938-02-17

Applicant: RCA CORP

Inventor： JACOBUS BOERS CORNELIS

IPC: H03L1/00 ,  H03L1/02

CPC classification number: H03L1/02 ,  H03L1/00

公开(公告)号：US2206238A

公开(公告)日：1940-07-02

申请号：US13205037

申请日：1937-03-20

Applicant: LORENZ C AG

Inventor： HANS ROCHOW

IPC: H03L1/02

CPC classification number: H03L1/02

公开(公告)号：US2156056A

公开(公告)日：1939-04-25

申请号：US8968236

申请日：1936-07-08

Applicant: LORENZ C AG

Inventor： HEINRICH HORNUNG

IPC: H03L1/02

CPC classification number: H03L1/02

公开(公告)号：US12094553B2

公开(公告)日：2024-09-17

申请号：US17556363

申请日：2021-12-20

Applicant: Rambus Inc.

Inventor： Yohan U. Frans ,  Wayne F. Ellis ,  Akash Bansal

IPC: G11C7/22 ,  G01R23/02 ,  G06F13/16 ,  G11C8/18 ,  G11C29/02 ,  G11C29/50 ,  H03L1/02 ,  G01R23/15 ,  G01R35/00 ,  G06F1/08 ,  G06F1/12 ,  G06F11/16 ,  G11C7/04

CPC classification number: G11C29/50012 ,  G01R23/02 ,  G06F13/1689 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/18 ,  G11C29/023 ,  G11C29/028 ,  H03L1/02 ,  G01R23/15 ,  G01R35/005 ,  G06F1/08 ,  G06F1/12 ,  G06F11/1604 ,  G11C7/04 ,  G11C2207/2254

Abstract: The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a memory device (or multiple devices) which includes a clock distribution circuit and an oscillator circuit which can generate a frequency, wherein a change in the frequency is indicative of a timing drift of the clock distribution circuit. The memory device also includes a measurement circuit which is configured to measure the frequency of the oscillator circuit.

公开(公告)号：US11750200B2

公开(公告)日：2023-09-05

申请号：US17624063

申请日：2020-06-19

Applicant: ZTE Corporation

Inventor： Jun Liu ,  Zhaobi Wei ,  Shan Wang ,  Pei Duan ,  Mengbi Lei

IPC: H03L7/081 ,  H03L7/08 ,  H03L7/10 ,  H03L1/02

CPC classification number: H03L7/081 ,  H03L1/02 ,  H03L7/0802 ,  H03L7/10

Abstract: Provided is a phase-locked loop circuit, a method for configuring the same, and a communication device. The phase-locked loop circuit includes a phase-locked loop main circuit and a phase temperature compensation circuit. The phase temperature compensation circuit includes at least one phase delay unit connected to the phase-locked loop main circuit and configured to generate a phase shift as a result of a temperature change for cancelling out a phase shift generated by the phase-locked loop main circuit as a result of a temperature change.

公开(公告)号：US11747216B1

公开(公告)日：2023-09-05

申请号：US17543052

申请日：2021-12-06

Applicant: SiTime Coporation

Inventor： Michael H. Perrott ,  Shungneng Lee

IPC: G01K7/22 ,  G01K7/16 ,  H03B5/04 ,  H03B5/30 ,  H03H9/02 ,  H03L1/02 ,  G01K7/34 ,  G01K7/18 ,  G01K7/12

CPC classification number: G01K7/226 ,  G01K7/16 ,  G01K7/22 ,  G01K7/34 ,  H03B5/04 ,  H03B5/30 ,  H03H9/02244 ,  H03L1/02 ,  G01K7/12 ,  G01K7/186 ,  G01K2219/00

Abstract: The temperature-dependent resistance of a MEMS structure is compared with an effective resistance of a switched CMOS capacitive element to implement a high performance temperature sensor.

公开(公告)号：US11705912B2

公开(公告)日：2023-07-18

申请号：US17386774

申请日：2021-07-28

Applicant: Infineon Technologies AG

Inventor： Francesco Brandonisio

IPC: H03L7/099 ,  H03L7/093 ,  H03L1/02 ,  G05B13/04 ,  H03L1/00

CPC classification number: H03L7/0991 ,  G05B13/042 ,  H03L1/00 ,  H03L1/02 ,  H03L7/093 ,  H03L2207/50

Abstract: A tracking system for a digital Phase Locked Loop (PLL), the tracking system including a PLL model configured to emulate an actual internal PLL signal, wherein the emulation is based on another internal PLL signal received from the digital PLL and on an estimated analog PLL parameter of the PLL model; and a tracker configured to compare the emulated internal PLL signal with the actual internal PLL signal, and to update the estimated analog PLL parameter according to a minimization algorithm that minimizes a result of the comparison.