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    Non-volatile memory device and electronic apparatus
    71.
    发明授权
    Non-volatile memory device and electronic apparatus 有权
    非易失性存储器件和电子设备

    公开(公告)号：US09111642B2

    公开(公告)日：2015-08-18

    申请号：US14074159

    申请日：2013-11-07

    Applicant: SEIKO EPSON CORPORATION

    Inventor： Masataka Kazuno

    IPC: G11C7/00 ,  G11C29/02 ,  G11C29/36 ,  G11C29/38 ,  G11C29/44

    CPC classification number: G11C29/026 ,  G11C29/36 ,  G11C29/38 ,  G11C29/44

    Abstract: A non-volatile memory device is provided, which includes a first block for storing a first data group including a test data, a second block for storing a second data group including a complementary data to the first data group, a differential sense amplifier for generating an output value based on a difference between two input signals, a diagnostic circuit for performing a failure diagnosis using a value from the differential sense amplifier, and a control circuit which performs control such that a signal based on the test data and the complementary data is set to the input signal of the differential sense amplifier and the diagnostic circuit executes a failure diagnosis of the differential sense amplifier. The non-volatile memory device performs a failure diagnosis with high reliability capable of distinguishing between a failure of sense amplifier and a failure of a memory cell.

    Abstract translation: 提供了一种非易失性存储器件，其包括用于存储包括测试数据的第一数据组的第一块，用于存储包括与第一数据组的互补数据的第二数据组的第二块，用于产生 基于两个输入信号之间的差的输出值，使用来自差分读出放大器的值执行故障诊断的诊断电路和执行基于测试数据和辅助数据的信号的控制的控制电路 设置为差分读出放大器的输入信号，诊断电路执行差动读出放大器的故障诊断。 非易失性存储器件执行高可靠性的故障诊断，能够区分读出放大器的故障和存储器单元的故障。

    SEMICONDUCTOR DEVICES
    72.
    发明申请
    SEMICONDUCTOR DEVICES 有权
    半导体器件

    公开(公告)号：US20150221397A1

    公开(公告)日：2015-08-06

    申请号：US14174572

    申请日：2014-02-06

    Applicant: SK hynix Inc.

    Inventor： Kwan Weon KIM

    IPC: G11C29/36 ,  G06F11/10

    CPC classification number: G11C29/36 ,  G11C2029/3602

    Abstract: A semiconductor device includes a normal test signal generator and a termination signal generator. The normal test signal generator is suitable for generating a first enablement signal and a first pulse signal in response to an external command signal when a first code signal and a second code signal have a predetermined logic combination. Further, the normal test signal generator is suitable for decoding a first test address signal and a second test address signal to generate first to fourth normal test signals. The termination signal generator is suitable for receiving the first pulse signal during an enablement period of the first enablement signal to generate a first termination signal which is enabled when a predetermined signal among the first to fourth normal test signals is generated.

    Abstract translation: 半导体器件包括正常测试信号发生器和终端信号发生器。 当第一代码信号和第二代码信号具有预定的逻辑组合时，正常测试信号发生器适用于响应于外部命令信号产生第一使能信号和第一脉冲信号。 此外，正常测试信号发生器适用于解码第一测试地址信号和第二测试地址信号以产生第一至第四正常测试信号。 终端信号发生器适于在第一使能信号的使能周期期间接收第一脉冲信号，以产生当产生第一至第四正常测试信号中的预定信号时使能的第一终端信号。

    TESTING ELECTRONIC MEMORIES BASED ON FAULT AND TEST ALGORITHM PERIODICITY
    74.
    发明申请
    TESTING ELECTRONIC MEMORIES BASED ON FAULT AND TEST ALGORITHM PERIODICITY 有权
    基于故障和测试算法周期测试电子记忆

    公开(公告)号：US20140380107A1

    公开(公告)日：2014-12-25

    申请号：US14484736

    申请日：2014-09-12

    Applicant: Synopsys, Inc.

    Inventor： Aram Hakhumyan ,  Gurgen Harutyunyan ,  Samvel Shoukourian ,  Valery Vardanian ,  Yervant Zorian

    IPC: G11C29/18 ,  G06F11/27

    CPC classification number: G11C29/18 ,  G06F11/27 ,  G11C29/10 ,  G11C29/16 ,  G11C29/36 ,  G11C2029/0405

    Abstract: An integrated circuit includes a memory and a memory test circuit, which when invoked to test the memory, is configured to generate one or more March tests applied to the memory. The memory test circuit is further configured to construct a table including a first index, a second index, and a first March test of the one or more March tests. The first index is associated with one or more families each characterized by a different length of the one or more March tests. The second index is associated with one or more mechanisms each characterized by a different property of the one or more March tests. The memory test circuit is further configured to generate a second March test from the first March test.

    Abstract translation: 集成电路包括存储器和存储器测试电路，当被调用以测试存储器时，被配置为产生施加到存储器的一个或多个3月测试。 存储器测试电路还被配置为构建包括一个或多个三月测试的第一索引，第二索引和第一March测试的表。 第一个索引与一个或多个家庭相关联，每个家庭的特征在于一个或多个三月份测试的不同长度。 第二个索引与一个或多个机制相关联，每个机制的特征在于一个或多个三月测试的不同属性。 存储器测试电路还被配置为从3月初测试产生第二次March测试。

    Autorecovery after manufacturing/system integration
    75.
    发明授权
    Autorecovery after manufacturing/system integration 有权
    制造/系统集成后的自动恢复

    公开(公告)号：US08904250B2

    公开(公告)日：2014-12-02

    申请号：US13767389

    申请日：2013-02-14

    Applicant: Micron Technology, Inc.

    Inventor： Francesco Falanga ,  Victor Tsai

    IPC: G11C29/00 ,  G11C29/44

    CPC classification number: G11C29/38 ,  G11C16/0483 ,  G11C16/3418 ,  G11C29/36 ,  G11C29/4401 ,  G11C29/52 ,  G11C2029/0407 ,  G11C2029/0409

    Abstract: Testing methods in a pre-programmed memory device after it has been assembled into a final customer platform include issuing a self-test command to the memory device, the memory device reporting results of a self-test of pre-programmed data executed responsive to receiving the self-test command, and issuing a self-repair command responsive to the results indicating repair of the pre-programmed data is needed.

    Abstract translation: 预先编程的存储器件中的测试方法已经被组装到最终的客户平台中之后，包括向存储器件发出自检命令，该存储器件报告响应于接收执行的预编程数据的自检的结果 自检命令，并且响应于指示预编程数据的修复的结果发出自修复命令。

    TESTING OF SRAMS
    77.
    发明申请
    TESTING OF SRAMS 有权
    SRAMS测试

    公开(公告)号：US20140136909A1

    公开(公告)日：2014-05-15

    申请号：US13672799

    申请日：2012-11-09

    Applicant: ORACLE INTERNATIONAL CORPORATION

    Inventor： Ali VAHIDSAFA ,  Sriram ANANDAKUMAR ,  Gaurav AGARWAL

    IPC: G11C29/00 ,  G06F11/16

    CPC classification number: G11C29/36 ,  G11C11/41 ,  G11C29/1201 ,  G11C29/14 ,  G11C2029/5602

    Abstract: Systems, methods, and other embodiments associated with at-speed testing of static random access memory (SRAM) are described. In one embodiment, a method includes loading, into a multi-stage pipeline of memory devices, a control pattern for testing a static random access memory (SRAM). The SRAM is tested by generating a test input that is based, at least in part, on the control pattern from the multi-stage pipeline of flip-flops. The test input is provided to the SRAM over a series of clock cycles that are at a core clock speed of the SRAM.

    Abstract translation: 描述了与静态随机存取存储器（SRAM）的高速测试相关联的系统，方法和其它实施例。 在一个实施例中，一种方法包括将存储器设备的多级流水线加载到用于测试静态随机存取存储器（SRAM）的控制模式。 通过产生至少部分地基于来自触发器的多级流水线的控制模式的测试输入来测试SRAM。 测试输入通过处于SRAM的核心时钟速度的一系列时钟周期提供给SRAM。

    SEMICONDUCTOR MEMORY DEVICE INCLUDING SELF-CONTAINED TEST UNIT AND TEST METHOD THEREOF
    78.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE INCLUDING SELF-CONTAINED TEST UNIT AND TEST METHOD THEREOF 审中-公开
    包含自测试单元的半导体存储器件及其测试方法

    公开(公告)号：US20130326295A1

    公开(公告)日：2013-12-05

    申请号：US13620419

    申请日：2012-09-14

    Applicant: Tae Ho JEON ,  Junw Seop JUNG ,  Sung Hyun JUNG

    Inventor： Tae Ho JEON ,  Junw Seop JUNG ,  Sung Hyun JUNG

    IPC: G11C29/10

    CPC classification number: G11C29/36 ,  G11C2029/3602

    Abstract: A semiconductor memory device is configured to internally perform a test operation utilizing a random data pattern. The semiconductor memory device includes a random data pattern test unit that operates under control of on-board control logic that also manages normal operation of the semiconductor memory device. The control logic controls test operation of the semiconductor memory device in response to simple commands received from an external device. Therefore, the test time may be reduced more than when a test is entirely controlled by an external device. Furthermore, since the external device does not need to manage the random data pattern, the test cost may be reduced more than when a test is performed under control of the external device.

    Abstract translation: 半导体存储器件被配置为在内部执行利用随机数据模式的测试操作。 半导体存储器件包括随机数据模式测试单元，其在还管理半导体存储器件的正常操作的板载控制逻辑的控制下操作。 控制逻辑响应于从外部设备接收到的简单命令来控制半导体存储器件的测试操作。 因此，当测试完全由外部设备控制时，测试时间可能会降低。 此外，由于外部设备不需要管理随机数据模式，所以与在外部设备的控制下进行测试时相比，可以降低测试成本。

    NON-VOLATILE MEMORY DEVICE
    80.
    发明申请
    NON-VOLATILE MEMORY DEVICE 有权
    非易失性存储器件

    公开(公告)号：US20130166823A1

    公开(公告)日：2013-06-27

    申请号：US13474917

    申请日：2012-05-18

    Applicant: In-Suk YUN

    Inventor： In-Suk YUN

    IPC: G06F12/02

    CPC classification number: G11C29/36 ,  G11C16/10

    Abstract: A non-volatile memory device includes a plurality of bit lines; a plurality of page buffers corresponding to the bit lines, respectively, and configured to each store a write data; and a control circuit configured to control at least one page buffer of the plurality of page buffers to store the write data of a first logic level and control other ones of the plurality of page buffers to store the write data of a second logic level, wherein the control circuit is further configured to select the at least one page buffer based on an address inputted to the control circuit. Since write data of diverse patterns may be generated within a non-volatile memory device by using a portion of the bits of the address, a test operation of the non-volatile memory device may be performed within a short time.

    Abstract translation: 非易失性存储器件包括多个位线; 分别对应于位线的多个页面缓冲器，并且被配置为分别存储写入数据; 以及控制电路，被配置为控制所述多个页面缓冲器中的至少一个页面缓冲器以存储第一逻辑电平的写入数据，并且控制所述多个页面缓冲器中的其他页面缓冲器以存储第二逻辑电平的写入数据，其中 所述控制电路还被配置为基于输入到所述控制电路的地址来选择所述至少一个寻呼缓冲器。 由于可以通过使用地址的位的一部分在非易失性存储器件内产生不同图案的写入数据，所以可以在短时间内执行非易失性存储器件的测试操作。

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