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公开(公告)号：US08898377B2
公开(公告)日：2014-11-25
申请号：US13603364
申请日：2012-09-04
Applicant: Tae Ho Jeon , Won Sun Park
Inventor： Tae Ho Jeon , Won Sun Park
CPC classification number: G11C16/10 , G06F7/764 , G06F11/0703 , G06F12/1408 , G06F2212/1036 , G11C7/1006 , G11C16/0483 , G11C16/34 , G11C16/3418
Abstract: A semiconductor device includes a first operation circuit configured to generate addition data by adding a column address and a page address and output a remainder obtained by dividing the addition data by a set value as seed data, a mask data output circuit configured to output mask data corresponding to the respective seed data, and a second operation circuit configured to generate random data by performing a logic operation on the mask data and program data corresponding to the column and page addresses.
Abstract translation: 半导体器件包括：第一操作电路，被配置为通过将列地址和页地址相加产生附加数据，并将通过将加法数据除以设定值而获得的余数作为种子数据，掩模数据输出电路，被配置为输出掩模数据 以及第二操作电路，被配置为通过对对应于列和页地址的掩码数据和程序数据执行逻辑运算来生成随机数据。
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2.发明授权Semiconductor memory device, operating method thereof, and data storage apparatus including the same 有权半导体存储器件及其操作方法以及包括该半导体存储器件的数据存储设备
公开(公告)号：US08867283B2
公开(公告)日：2014-10-21
申请号：US13469847
申请日：2012-05-11
Applicant: Won Sun Park , Tae Ho Jeon
Inventor： Won Sun Park , Tae Ho Jeon
CPC classification number: G11C7/10 , G11C7/00 , G11C7/1006 , G11C7/1012 , G11C7/22 , G11C16/10 , G11C16/26 , G11C16/3418
Abstract: A semiconductor memory device includes memory cells arranged at regions where word lines and bit lines cross each other; a randomizing and de-randomizing circuit configured to perform a first randomizing operation on data to be programmed to the memory cells, based on a seed value, so as to generate first randomized data; a data reading/writing circuit configured to perform a second randomizing operation on the first randomized data using a data inverting operation so as to generate second randomized data and program the second randomized data to the memory cells; and a control logic configured to control the randomizing and de-randomizing circuit and the data reading/writing circuit.
Abstract translation: 半导体存储器件包括布置在字线和位线彼此交叉的区域处的存储单元; 一种随机化和去随机化电路，被配置为基于种子值对要编程到存储器单元的数据执行第一随机化操作，以便生成第一随机化数据; 数据读/写电路，被配置为使用数据反转操作对所述第一随机化数据执行第二随机化操作，以便生成第二随机数据并将所述第二随机数据编程到所述存储器单元; 以及控制逻辑，被配置为控制随机化和去随机化电路和数据读/写电路。
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3.发明申请SEMICONDUCTOR MEMORY DEVICE, OPERATING METHOD THEREOF, AND DATA STORAGE APPARATUS INCLUDING THE SAME 有权半导体存储器件及其操作方法和包括其的数据存储器件
公开(公告)号：US20130121090A1
公开(公告)日：2013-05-16
申请号：US13469847
申请日：2012-05-11
Applicant: Won Sun PARK , Tae Ho JEON
Inventor： Won Sun PARK , Tae Ho JEON
IPC: G11C7/00
CPC classification number: G11C7/10 , G11C7/00 , G11C7/1006 , G11C7/1012 , G11C7/22 , G11C16/10 , G11C16/26 , G11C16/3418
Abstract: A semiconductor memory device includes memory cells arranged at regions where word lines and bit lines cross each other; a randomizing and de-randomizing circuit configured to perform a first randomizing operation on data to be programmed to the memory cells, based on a seed value, so as to generate first randomized data; a data reading/writing circuit configured to perform a second randomizing operation on the first randomized data using a data inverting operation so as to generate second randomized data and program the second randomized data to the memory cells; and a control logic configured to control the randomizing and de-randomizing circuit and the data reading/writing circuit.
Abstract translation: 半导体存储器件包括布置在字线和位线彼此交叉的区域处的存储单元; 一种随机化和去随机化电路，被配置为基于种子值对要编程到存储器单元的数据执行第一随机化操作，以便生成第一随机化数据; 数据读/写电路，被配置为使用数据反转操作对所述第一随机化数据执行第二随机化操作，以便生成第二随机数据并将所述第二随机数据编程到所述存储器单元; 以及控制逻辑，被配置为控制随机化和去随机化电路和数据读/写电路。
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公开(公告)号：US20130083619A1
公开(公告)日：2013-04-04
申请号：US13603364
申请日：2012-09-04
Applicant: Tae Ho Jeon , Won Sun Park
Inventor： Tae Ho Jeon , Won Sun Park
IPC: G11C8/00
CPC classification number: G11C16/10 , G06F7/764 , G06F11/0703 , G06F12/1408 , G06F2212/1036 , G11C7/1006 , G11C16/0483 , G11C16/34 , G11C16/3418
Abstract: A semiconductor device includes a first operation circuit configured to generate addition data by adding a column address and a page address and output a remainder obtained by dividing the addition data by a set value as seed data, a mask data output circuit configured to output mask data corresponding to the respective seed data, and a second operation circuit configured to generate random data by performing a logic operation on the mask data and program data corresponding to the column and page addresses.
Abstract translation: 半导体器件包括：第一操作电路，被配置为通过将列地址和页地址相加产生附加数据，并将通过将加法数据除以设定值而获得的余数作为种子数据，掩模数据输出电路，被配置为输出掩模数据 以及第二操作电路，被配置为通过对对应于列和页地址的掩码数据和程序数据执行逻辑运算来生成随机数据。
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公开(公告)号：US20120269007A1
公开(公告)日：2012-10-25
申请号：US13451110
申请日：2012-04-19
Applicant: In Gon YANG , Duck Ju KIM , Jae Won CHA , Sung Hoon AHN , Tae Ho JEON
Inventor： In Gon YANG , Duck Ju KIM , Jae Won CHA , Sung Hoon AHN , Tae Ho JEON
CPC classification number: G11C7/00 , G11C7/10 , G11C11/5642 , G11C16/0483
Abstract: A semiconductor memory device includes a memory cell array configured to include memory cells, peripheral circuits configured to read out data stored in a selected memory cell in a read operation, and a controller configured to control the peripheral circuits so that the peripheral circuits sense a voltage level of the bit line when a first read voltage of the read voltages is supplied to the word line and the peripheral circuits sense voltage levels of the bit line when a second read voltage lower than the first read voltage by a specific level and a third read voltage higher than the first read voltage by the specific level are supplied to the word line in order to determine whether a threshold voltage of the selected memory cell falls within a set voltage distribution in the read operation.
Abstract translation: 半导体存储器件包括：存储单元阵列，被配置为包括存储器单元，外围电路，被配置为在读取操作中读出存储在选择的存储单元中的数据;以及控制器，被配置为控制外围电路，使得外围电路感测电压 当读取电压的第一读取电压被提供给字线时，位线的电平，并且当低于第一读取电压的第二读取电压达到特定电平和第三读取时，外围电路检测位线的电压电平 将高于第一读取电压的特定电平的电压提供给字线，以便确定所选择的存储器单元的阈值电压是否落在读取操作中的设置电压分布内。
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6.发明申请SEMICONDUCTOR MEMORY DEVICE INCLUDING SELF-CONTAINED TEST UNIT AND TEST METHOD THEREOF 审中-公开包含自测试单元的半导体存储器件及其测试方法
公开(公告)号：US20130326295A1
公开(公告)日：2013-12-05
申请号：US13620419
申请日：2012-09-14
Applicant: Tae Ho JEON , Junw Seop JUNG , Sung Hyun JUNG
Inventor： Tae Ho JEON , Junw Seop JUNG , Sung Hyun JUNG
IPC: G11C29/10
CPC classification number: G11C29/36 , G11C2029/3602
Abstract: A semiconductor memory device is configured to internally perform a test operation utilizing a random data pattern. The semiconductor memory device includes a random data pattern test unit that operates under control of on-board control logic that also manages normal operation of the semiconductor memory device. The control logic controls test operation of the semiconductor memory device in response to simple commands received from an external device. Therefore, the test time may be reduced more than when a test is entirely controlled by an external device. Furthermore, since the external device does not need to manage the random data pattern, the test cost may be reduced more than when a test is performed under control of the external device.
Abstract translation: 半导体存储器件被配置为在内部执行利用随机数据模式的测试操作。 半导体存储器件包括随机数据模式测试单元，其在还管理半导体存储器件的正常操作的板载控制逻辑的控制下操作。 控制逻辑响应于从外部设备接收到的简单命令来控制半导体存储器件的测试操作。 因此，当测试完全由外部设备控制时，测试时间可能会降低。 此外，由于外部设备不需要管理随机数据模式，所以与在外部设备的控制下进行测试时相比，可以降低测试成本。
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公开(公告)号：US20110184497A1
公开(公告)日：2011-07-28
申请号：US13003800
申请日：2009-07-14
Applicant: Sung June Kim , Choong Jae Lee , Tae Ho Jeon , Soon Kwan An , William J. Heetderks
Inventor： Sung June Kim , Choong Jae Lee , Tae Ho Jeon , Soon Kwan An , William J. Heetderks
CPC classification number: A61N1/3605 , A61F2/0077 , A61N1/375 , A61N1/3787
Abstract: Disclosed is a neural stimulator for neural prosthesis: including a power receiver which receives power from outside and supplies the received power to a circuitry including an electrical signal generator; the electrical signal generator which generates a neural stimulating electrical signal; and a casing which protects the power receiver and the electrical signal generator from bodily fluid, wherein the power supplied by the power receiver to the circuitry including the electrical signal generator is AC logic power. In accordance with this disclosure, a neural stimulator with reduced production cost, simplified production process and reduced size, as compared with those of the related art, while being safe, may be provided.
Abstract translation: 公开了一种用于神经假体的神经刺激器：包括从外部接收功率并将接收的功率提供给包括电信号发生器的电路的功率接收器; 产生神经刺激电信号的电信号发生器; 以及保护功率接收器和电信号发生器免受体液的外壳，其中由电力接收器提供给包括电信号发生器的电路的电力是AC逻辑电力。 根据本公开，可以提供与安全的相关技术相比，具有降低生产成本，简化生产过程和减小尺寸的神经刺激器。
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公开(公告)号：US08902674B2
公开(公告)日：2014-12-02
申请号：US13451110
申请日：2012-04-19
Applicant: In Gon Yang , Duck Ju Kim , Jae Won Cha , Sung Hoon Ahn , Tae Ho Jeon
Inventor： In Gon Yang , Duck Ju Kim , Jae Won Cha , Sung Hoon Ahn , Tae Ho Jeon
CPC classification number: G11C7/00 , G11C7/10 , G11C11/5642 , G11C16/0483
Abstract: A semiconductor memory device includes a memory cell array configured to include memory cells, peripheral circuits configured to read out data stored in a selected memory cell in a read operation, and a controller configured to control the peripheral circuits so that the peripheral circuits sense a voltage level of the bit line when a first read voltage of the read voltages is supplied to the word line and the peripheral circuits sense voltage levels of the bit line when a second read voltage lower than the first read voltage by a specific level and a third read voltage higher than the first read voltage by the specific level are supplied to the word line in order to determine whether a threshold voltage of the selected memory cell falls within a set voltage distribution in the read operation.
Abstract translation: 半导体存储器件包括：存储单元阵列，被配置为包括存储器单元，外围电路，被配置为在读取操作中读出存储在选择的存储单元中的数据;以及控制器，被配置为控制外围电路，使得外围电路感测电压 当读取电压的第一读取电压被提供给字线时，位线的电平，并且当低于第一读取电压的第二读取电压达到特定电平和第三读取时，外围电路检测位线的电压电平 将高于第一读取电压的特定电平的电压提供给字线，以便确定所选择的存储器单元的阈值电压是否落在读取操作中的设置电压分布内。
